Re: [Intel-wired-lan] Opportunistic S0ix blocked by e1000e when ethernet is in use

[Neftin, Sasha]

On 6/24/2019 18:06, Kai-Heng Feng wrote:
> at 19:56, Neftin, Sasha <sasha.neftin@xxxxxxxxx> wrote:
>
> > On 6/24/2019 10:03, Kai-Heng Feng wrote:
> > > Hi Jeffrey,
> > > at 19:08, Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx> wrote:
> > > > Hi Jeffrey,
> > > >
> > > > There are several platforms that uses e1000e canât enter 
> > > > Opportunistic S0ix (PC10) when the ethernet has a link partner.
> > > >
> > > > This behavior also exits in out-of-tree e1000e driver 3.4.2.1, but 
> > > > seems like 3.4.2.3 fixes the issue.
> > > >
> > > > A quick diff between the two versions shows that this code section 
> > > > may be our solution:
> > > >
> > > > ÂÂÂÂÂÂÂ /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan 
> > > > function
> > > > ÂÂÂÂÂÂÂÂ * may occur during global reset and cause system hang.
> > > > ÂÂÂÂÂÂÂÂ * Configuration space access creates the needed delay.
> > > > ÂÂÂÂÂÂÂÂ * Write to E1000_STRAP RO register 
> > > > E1000_PCI_VENDOR_ID_REGISTER value
> > > > ÂÂÂÂÂÂÂÂ * insures configuration space read is done before global 
> > > > reset.
> > > > ÂÂÂÂÂÂÂÂ */
> > > > ÂÂÂÂÂÂÂ pci_read_config_word(hw->adapter->pdev, 
> > > > E1000_PCI_VENDOR_ID_REGISTER,
> > > > ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &pci_cfg);
> > > > ÂÂÂÂÂÂÂ ew32(STRAP, pci_cfg);
> > > > ÂÂÂÂÂÂÂ e_dbg("Issuing a global reset to ich8lan\n");
> > > > ÂÂÂÂÂÂÂ ew32(CTRL, (ctrl | E1000_CTRL_RST));
> > > > ÂÂÂÂÂÂÂ /* cannot issue a flush here because it hangs the hardware */
> > > > ÂÂÂÂÂÂÂ msleep(20);
> > > >
> > > > ÂÂÂÂÂÂÂ /* Configuration space access improve HW level time sync 
> > > > mechanism.
> > > > ÂÂÂÂÂÂÂÂ * Write to E1000_STRAP RO register 
> > > > E1000_PCI_VENDOR_ID_REGISTER
> > > > ÂÂÂÂÂÂÂÂ * value to insure configuration space read is done
> > > > ÂÂÂÂÂÂÂÂ * before any access to mac register.
> > > > ÂÂÂÂÂÂÂÂ */
> > > > ÂÂÂÂÂÂÂ pci_read_config_word(hw->adapter->pdev, 
> > > > E1000_PCI_VENDOR_ID_REGISTER,
> > > > ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &pci_cfg);
> > > > ÂÂÂÂÂÂÂ ew32(STRAP, pci_cfg);
> > > Turns out the "extra sauceâ is not this part, itâs called âDynamic 
> > > LTR supportâ.
> > > >>
> > > > Is there any plan to support this in the upstream kernel?
> > > Is there any plan to support Dynamic LTR in upstream e1000e?
> > Dynamic LTR is not stable solution. So, we can not put this solution 
> > to upstream. I hope we will be able to fix this in HW for a future 
> > projects.
>
> Does this mean current generation hardware wonât get the fix?
Current HW have a limitation. Please, try follow workaround on your 
platform: echo 3 > /sys/kernel/debug/pmc_core/ltr_ignore
> >> S0ix support is under discussion with our architecture. We will try
> > enable S0ix in our e1000e OOT driver as first step.
>
> Is it possible to add Dynamic LTR as an option so users and downstream 
> distros can still benefit from it?
As I said before, this is not a stable solution. No guarantee that HW 
will work as properly.
> Kai-Heng
>
> > > Kai-Heng
> > > > Kai-Heng
> > > _______________________________________________
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> > > Intel-wired-lan@xxxxxxxxxx
> > > https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
> >
> > Thanks
> > Sasha