Re: [PATCH] clk: socfpga: stratix10: add additional clocks needed for the NAND IP

[Stephen Boyd]

Quoting Dinh Nguyen (2019-06-24 14:47:10)
> The nand_clk is actually called the nand_x_clk and the parent is the
> l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
> nand_x_clk and has a fixed divider of 4. The same is true for the
> nand_ecc_clk.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---

Applied to clk-next