Re: [PATCH v2 1/2] mtd: nand: Add Cadence NAND controller driver

[Piotr Sroka]

The 07/01/2019 12:04, Miquel Raynal wrote:
> EXTERNAL MAIL
>
>
> Hi Piotr,
>
> Piotr Sroka <piotrs@xxxxxxxxxxx> wrote on Mon, 1 Jul 2019 10:51:45
> +0100:
>
>
> [...]
> > >> >> >
> > >> >> >This driver is way too massive, I am pretty sure it can shrink a
> > >> >> >little bit more.
> > >> >> >[...]
> > >> >> >
> > >> >> I will try to make it shorer but it will be difucult to achive. It is because - there are a lot of calculation needed for PHY      - ECC are interleaved with data (like on marvell-nand or gpmi-nand).
> > >> >>    Therefore:    + RAW mode is complicated    + protecting BBM increases number of lines of source code
> > >> >> - need to support two DMA engines internal and external (slave) We will see on next patch version what is the result.      That page layout looks:
> > >> >
> > >> >Maybe you don't need to support both internal and external DMA?
> > >> >
> > >> >I am pretty sure there are rooms for size reduction.
> > >>
> > >> I describe how it works in general and maybe you help me chose better solution.
> > >>
> > >> HW controller can work in 3 modes. PIO - can work in master or slave DMA
> > >> CDMA - needs Master DMA for accessing command descriptors.
> > >> Generic mode - can use only Slave DMA.
> > >>
> > >> Generic mode is neccessery to implement functions other than page
> > >> program, page read, block erase. So it is essential. I cannot avoid
> > >> to use Slave DMA.
> > >
> > >This deserves a nice comment at the top.
> > Ok I will add the modes description to cover letter. >
>
> Not only to the cover letter: People read the code. Interested people
> might also read the commit log which is quite easy to find. The cover
> letter however will just disappear in the history of the Internet. I
> would rather prefer you explain how the IP works at the top of the
> driver.
So I will add the modes description to both cover letter and 
at the top of the driver. 
> Thanks,
> MiquÃl

Thanks,
Piotr