Re: [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features

[Vidya Sagar]

On 7/5/2019 7:16 PM, Vidya Sagar wrote:
Bjorn,
Apologies for pinging again about this.
Can you please provide Ack for this change so that Lorenzo can pick up this series?

Thanks,
Vidya Sagar

> On 7/1/2019 6:09 PM, Vidya Sagar wrote:
> Bjorn,
> Can you please provide Ack for this patch?
>
> Thanks,
> Vidya Sagar
>
> > Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
> > features.
> >
> > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> > Reviewed-by: Thierry Reding <treding@xxxxxxxxxx>
> > ---
> > Changes since [v11]:
> > * None
> >
> > Changes since [v10]:
> > * None
> >
> > Changes since [v9]:
> > * None
> >
> > Changes since [v8]:
> > * None
> >
> > Changes since [v7]:
> > * None
> >
> > Changes since [v6]:
> > * None
> >
> > Changes since [v5]:
> > * None
> >
> > Changes since [v4]:
> > * None
> >
> > Changes since [v3]:
> > * None
> >
> > Changes since [v2]:
> > * Updated commit message and description to explicitly mention that defines are
> > ÂÂ added only for some of the features and not all.
> >
> > Changes since [v1]:
> > * None
> >
> > Â include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
> > Â 1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index f28e562d7ca8..1c79f6a097d2 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -713,7 +713,9 @@
> > Â #define PCI_EXT_CAP_ID_DPCÂÂÂ 0x1DÂÂÂ /* Downstream Port Containment */
> > Â #define PCI_EXT_CAP_ID_L1SSÂÂÂ 0x1EÂÂÂ /* L1 PM Substates */
> > Â #define PCI_EXT_CAP_ID_PTMÂÂÂ 0x1FÂÂÂ /* Precision Time Measurement */
> > -#define PCI_EXT_CAP_ID_MAXÂÂÂ PCI_EXT_CAP_ID_PTM
> > +#define PCI_EXT_CAP_ID_DLFÂÂÂ 0x25ÂÂÂ /* Data Link Feature */
> > +#define PCI_EXT_CAP_ID_PLÂÂÂ 0x26ÂÂÂ /* Physical Layer 16.0 GT/s */
> > +#define PCI_EXT_CAP_ID_MAXÂÂÂ PCI_EXT_CAP_ID_PL
> > Â #define PCI_EXT_CAP_DSN_SIZEOFÂÂÂ 12
> > Â #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
> > @@ -1053,4 +1055,22 @@
> >  #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
> > Â #define PCI_L1SS_CTL2ÂÂÂÂÂÂÂ 0x0cÂÂÂ /* Control 2 Register */
> > +/* Data Link Feature */
> > +#define PCI_DLF_CAPÂÂÂÂÂÂÂ 0x04ÂÂÂ /* Capabilities Register */
> > +#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
> > +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
> > +#define PCI_DLF_STSÂÂÂÂÂÂÂ 0x08ÂÂÂ /* Status Register */
> > +#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
> > +#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
> > +
> > +/* Physical Layer 16.0 GT/s */
> > +#define PCI_PL_16GT_CAPÂÂÂÂÂÂÂ 0x04ÂÂÂ /* Capabilities Register */
> > +#define PCI_PL_16GT_CTRLÂÂÂ 0x08ÂÂÂ /* Control Register */
> > +#define PCI_PL_16GT_STSÂÂÂÂÂÂÂ 0x0cÂÂÂ /* Status Register */
> > +#define PCI_PL_16GT_LDPM_STSÂÂÂ 0x10ÂÂÂ /* Local Data Parity Mismatch Status Register */
> > +#define PCI_PL_16GT_FRDPM_STSÂÂÂ 0x14ÂÂÂ /* First Retimer Data Parity Mismatch Status Register */
> > +#define PCI_PL_16GT_SRDPM_STSÂÂÂ 0x18ÂÂÂ /* Second Retimer Data Parity Mismatch Status Register */
> > +#define PCI_PL_16GT_RSVDÂÂÂ 0x1CÂÂÂ /* Reserved */
> > +#define PCI_PL_16GT_LE_CTRLÂÂÂ 0x20ÂÂÂ /* Lane Equalization Control Register */
> > +
> > Â #endif /* LINUX_PCI_REGS_H */