[PATCH] MIPS: perf events: handle switch statement falling through warnings

[Stephen Rothwell]

Now that we build with -Wimplicit-fallthrough=3, some warnings are
produced in the arch/mips perf events code that are promoted to errors:

 arch/mips/kernel/perf_event_mipsxx.c:792:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:795:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:798:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:1407:6: error: this statement may fall through [-Werror=implicit-fallthrough=]

Assume the fall throughs are deliberate amd annotate/eliminate them.

Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Ingo Molnar <mingo@xxxxxxxxxx>
Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
Cc: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Namhyung Kim <namhyung@xxxxxxxxxx>
Cc: Gustavo A. R. Silva <gustavo@xxxxxxxxxxxxxx>
Cc: Kees Cook <keescook@xxxxxxxxxxxx>
Signed-off-by: Stephen Rothwell <sfr@xxxxxxxxxxxxxxxx>
---
 arch/mips/kernel/perf_event_mipsxx.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

I haven't even build tested this, sorry, but will add it to linux-next
tomorrow.  It should be no worse than the current state :-)

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index e0ebaa0a333e..40106731e97e 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -790,15 +790,19 @@ static void reset_counters(void *arg)
 	case 4:
 		mipsxx_pmu_write_control(3, 0);
 		mipspmu.write_counter(3, 0);
+		/* fall through */
 	case 3:
 		mipsxx_pmu_write_control(2, 0);
 		mipspmu.write_counter(2, 0);
+		/* fall through */
 	case 2:
 		mipsxx_pmu_write_control(1, 0);
 		mipspmu.write_counter(1, 0);
+		/* fall through */
 	case 1:
 		mipsxx_pmu_write_control(0, 0);
 		mipspmu.write_counter(0, 0);
+		/* fall through */
 	}
 }
 
@@ -1379,7 +1383,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 	struct perf_sample_data data;
 	unsigned int counters = mipspmu.num_counters;
-	u64 counter;
+	unsigned int n;
 	int handled = IRQ_NONE;
 	struct pt_regs *regs;
 
@@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void)
 
 	perf_sample_data_init(&data, 0, 0);
 
-	switch (counters) {
-#define HANDLE_COUNTER(n)						\
-	case n + 1:							\
-		if (test_bit(n, cpuc->used_mask)) {			\
-			counter = mipspmu.read_counter(n);		\
-			if (counter & mipspmu.overflow) {		\
-				handle_associated_event(cpuc, n, &data, regs); \
-				handled = IRQ_HANDLED;			\
-			}						\
+	for (n = (counters > 4) ? 3 : (counters - 1); n >= 0; n--) {
+		u64 counter;
+
+		if (test_bit(n, cpuc->used_mask)) {
+			counter = mipspmu.read_counter(n);
+			if (counter & mipspmu.overflow) {
+				handle_associated_event(cpuc, n, &data, regs);
+				handled = IRQ_HANDLED;
+			}
 		}
-	HANDLE_COUNTER(3)
-	HANDLE_COUNTER(2)
-	HANDLE_COUNTER(1)
-	HANDLE_COUNTER(0)
 	}
 
 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
-- 
2.22.0

-- 
Cheers,
Stephen Rothwell

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