[PATCH v1 14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420

[Lukasz Luba]

Add ID to mout_sclk_cpll MUX to make possible children connection in
the DT.

Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2395b02ce8c5..6d1a0ef9172e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -696,7 +696,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 			CLK_SET_RATE_PARENT, 0),
 	MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
 			SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
-	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+	MUX(CLK_MOUT_SCLK_CPLL, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
 	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
 			mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
-- 
2.17.1