Re: [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges

[Vladimir Murzin]

Hi Marc,

On 8/6/19 11:01 AM, Marc Zyngier wrote:
> As is it usual for the GIC, it isn't disallowed to put together a system
> that is majorly inconsistent, with a distributor supporting the
> extended ranges while some of the CPUs don't.
> 
> Kindly tell the user that things are sailing isn't going to be smooth.
> 
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> ---
>  drivers/irqchip/irq-gic-v3.c       | 5 +++++
>  include/linux/irqchip/arm-gic-v3.h | 1 +
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index f53e58d398ba..334a10d9dbfb 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -1014,6 +1014,11 @@ static void gic_cpu_init(void)
>  
>  	gic_enable_redist(true);
>  
> +	WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
> +	     !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
> +	     "Distributor has extended ranges, but CPU%d doesn't\n",
> +	     smp_processor_id());
> +

Should such setup be tainted?

Cheers
Vladimir

>  	rbase = gic_data_rdist_sgi_base();
>  
>  	/* Configure SGIs/PPIs as non-secure Group-1 */
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 9ec3349dee04..5cc10cf7cb3e 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -496,6 +496,7 @@
>  #define ICC_CTLR_EL1_A3V_SHIFT		15
>  #define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
>  #define ICC_CTLR_EL1_RSS		(0x1 << 18)
> +#define ICC_CTLR_EL1_ExtRange		(0x1 << 19)
>  #define ICC_PMR_EL1_SHIFT		0
>  #define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
>  #define ICC_BPR0_EL1_SHIFT		0
>