Re: [PATCH v8 19/21] soc/tegra: pmc: Configure deep sleep control settings

[Dmitry Osipenko]

09.08.2019 20:24, Sowjanya Komatineni ÐÐÑÐÑ:
> 
> On 8/9/19 9:23 AM, Sowjanya Komatineni wrote:
>>
>> On 8/9/19 6:23 AM, Dmitry Osipenko wrote:
>>> 09.08.2019 2:46, Sowjanya Komatineni ÐÐÑÐÑ:
>>>> Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
>>>> timings which are platform specific that should be configured before
>>>> entering into deep sleep.
>>>>
>>>> Below are the timing specific configurations for deep sleep entry and
>>>> wakeup.
>>>> - Core rail power-on stabilization timer
>>>> - OSC clock stabilization timer after SOC rail power is stabilized.
>>>> - Core power off time is the minimum wake delay to keep the system
>>>> ÂÂ in deep sleep state irrespective of any quick wake event.
>>>>
>>>> These values depends on the discharge time of regulators and turn OFF
>>>> time of the PMIC to allow the complete system to finish entering into
>>>> deep sleep state.
>>>>
>>>> These values vary based on the platform design and are specified
>>>> through the device tree.
>>>>
>>>> This patch has implementation to configure these timings which are must
>>>> to have for proper deep sleep and wakeup operations.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
>>>> ---
>>>> Â drivers/soc/tegra/pmc.c | 13 ++++++++++++-
>>>> Â 1 file changed, 12 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>> index e013ada7e4e9..9a78d8417367 100644
>>>> --- a/drivers/soc/tegra/pmc.c
>>>> +++ b/drivers/soc/tegra/pmc.c
>>>> @@ -88,6 +88,8 @@
>>>> Â Â #define PMC_CPUPWRGOOD_TIMERÂÂÂÂÂÂÂ 0xc8
>>>> Â #define PMC_CPUPWROFF_TIMERÂÂÂÂÂÂÂ 0xcc
>>>> +#define PMC_COREPWRGOOD_TIMERÂÂÂÂÂÂÂ 0x3c
>>>> +#define PMC_COREPWROFF_TIMERÂÂÂÂÂÂÂ 0xe0
>>>> Â Â #define PMC_PWR_DET_VALUEÂÂÂÂÂÂÂ 0xe4
>>>> Â @@ -2277,7 +2279,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = {
>>>> Â Â static void tegra20_pmc_init(struct tegra_pmc *pmc)
>>>> Â {
>>>> -ÂÂÂ u32 value;
>>>> +ÂÂÂ u32 value, osc, pmu, off;
>>>> Â ÂÂÂÂÂ /* Always enable CPU power request */
>>>> ÂÂÂÂÂ value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>> @@ -2303,6 +2305,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
>>>> ÂÂÂÂÂ value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>> ÂÂÂÂÂ value |= PMC_CNTRL_SYSCLK_OE;
>>>> ÂÂÂÂÂ tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>> +
>>>> +ÂÂÂ osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
>>>> +ÂÂÂ pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
>>>> +ÂÂÂ off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
>>>> +ÂÂÂ if (osc && pmu)
>>>> +ÂÂÂÂÂÂÂ tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PMC_COREPWRGOOD_TIMER);
>>>> +ÂÂÂ if (off)
>>>> +ÂÂÂÂÂÂÂ tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
>>> The osc/pmu/off values are undefined if they are not defined in device-tree. I suppose this
>>> need to be corrected in tegra_pmc_parse_dt() if the values really matter even if LP0 suspend
>>> isn't supported in device-tree.
>>>
>>> And I'm also not sure what's wrong with setting 0 for the timers.
>>>
>> These settings are for SC7 only and will not have any impact in normal state.
> POR value for these timing registers is not 0 and has default timings based on chip design
> and on top of that based on platform HW components charge/discharge timings there's a need
> to increase these timings so support for programming these thru DT is needed and these
> values have effect only in LP0.

If it is legal to omit the timings in DT, then tegra_pmc_parse_dt() need to be corrected if
there is assumption of 0 meaning that values are undefined in DT.