Re: [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers

From: Paul Walmsley
Date: Tue Aug 13 2019 - 13:44:06 EST


Thomas, Jason, Marc,

On Tue, 13 Aug 2019, Christoph Hellwig wrote:

> When running in M-mode we still the S-mode plic handlers in the DT.
> Ignore them by setting the maximum threshold.
>
> Signed-off-by: Christoph Hellwig <hch@xxxxxx>

If you're happy with this, could one of you ack it so we can merge it
with the rest of this series through the RISC-V tree?

thanks

- Paul

> ---
> drivers/irqchip/irq-sifive-plic.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index cf755964f2f8..c72c036aea76 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -244,6 +244,7 @@ static int __init plic_init(struct device_node *node,
> struct plic_handler *handler;
> irq_hw_number_t hwirq;
> int cpu, hartid;
> + u32 threshold = 0;
>
> if (of_irq_parse_one(node, i, &parent)) {
> pr_err("failed to parse parent for context %d.\n", i);
> @@ -266,10 +267,16 @@ static int __init plic_init(struct device_node *node,
> continue;
> }
>
> + /*
> + * When running in M-mode we need to ignore the S-mode handler.
> + * Here we assume it always comes later, but that might be a
> + * little fragile.
> + */
> handler = per_cpu_ptr(&plic_handlers, cpu);
> if (handler->present) {
> pr_warn("handler already present for context %d.\n", i);
> - continue;
> + threshold = 0xffffffff;
> + goto done;
> }
>
> handler->present = true;
> @@ -279,8 +286,9 @@ static int __init plic_init(struct device_node *node,
> handler->enable_base =
> plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
>
> +done:
> /* priority must be > threshold to trigger an interrupt */
> - writel(0, handler->hart_base + CONTEXT_THRESHOLD);
> + writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
> for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
> plic_toggle(handler, hwirq, 0);
> nr_handlers++;
> --
> 2.20.1
>
>