Re: [PATCH v7 00/15] crypto: caam - Add i.MX8MQ support

[Horia Geanta]

On 8/13/2019 9:51 PM, Andrey Smirnov wrote:
> On Tue, Aug 13, 2019 at 6:59 AM Horia Geanta <horia.geanta@xxxxxxx> wrote:
>>
>> On 8/12/2019 11:08 PM, Andrey Smirnov wrote:
>>> Everyone:
>>>
>>> Picking up where Chris left off (I chatted with him privately
>>> beforehead), this series adds support for i.MX8MQ to CAAM driver. Just
>>> like [v1], this series is i.MX8MQ only.
>>>
>>> Feedback is welcome!
>>> Thanks,
>>> Andrey Smirnov
>>>
>>> Changes since [v6]:
>>>
>>>   - Fixed build problems in "crypto: caam - make CAAM_PTR_SZ dynamic"
>>>
>>>   - Collected Reviewied-by from Horia
>>>
>>>   - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
>>>     is changed to check 'caam_ptr_sz' instead of using 'caam_imx'
>>>
>>>   - Incorporated feedback for "crypto: caam - request JR IRQ as the
>>>     last step" and "crypto: caam - simplfy clock initialization"
>>>
>> FYI - the series does not apply cleanly on current cryptodev-2.6 tree.
>>
> 
> OK, sorry about that, will fix.
> 
Please also include the crypto DT node in v8 series - see patch below.

I would like to go with it through the cryptodev-2.6 tree,
to save one kernel release cycle.
This way kernel v5.4 would support CAAM on i.MX8MQ.

That's how we previously did for i.MX7ULP and Herbert and Shawn agreed.
Details (including who to Cc) here:
https://patchwork.kernel.org/patch/10978811/

-- >8 --

Subject: [PATCH] arm64: dts: imx8mq: add crypto node

Add node for CAAM - Cryptographic Acceleration and Assurance Module.

Signed-off-by: Horia Geantă <horia.geanta@xxxxxxx>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..197965dac505 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -728,6 +728,36 @@
 				status = "disabled";
 			};
 
+			crypto: crypto@30900000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				reg = <0x30900000 0x40000>;
+				ranges = <0 0x30900000 0x40000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_AHB>,
+					 <&clk IMX8MQ_CLK_IPG_ROOT>;
+				clock-names = "aclk", "ipg";
+
+				sec_jr0: jr0@1000 {
+					 compatible = "fsl,sec-v4.0-job-ring";
+					 reg = <0x1000 0x1000>;
+					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr1@2000 {
+					 compatible = "fsl,sec-v4.0-job-ring";
+					 reg = <0x2000 0x1000>;
+					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr2@3000 {
+					 compatible = "fsl,sec-v4.0-job-ring";
+					 reg = <0x3000 0x1000>;
+					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			i2c1: i2c@30a20000 {
 				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 				reg = <0x30a20000 0x10000>;
-- 
2.17.1