On Thu, Aug 22, 2019 at 2:32 AM Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> wrote:Sure, will update it.
Add YAML schemas for the reset controller on Intelcompatible:
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
---
.../bindings/reset/intel,syscon-reset.yaml | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index 000000000000..298c60085486
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
+
+properties:
+ compatible:
+ allOf:
+ - items:
+ - enum:
+ - intel,rcu-lgm
+ - syscon
items:
- const: intel,rcu-lgm
- const: syscon
Sure, will add the description.+Add a description with what each cell contains.
+ reg:
+ description: Reset controller register base address and size
+
+ intel,global-reset:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+ const: 2
+Add a:
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
additionalProperties: false
+
+examples:
+ - |
+ rcu0: reset-controller@00000000 {
+ compatible = "intel,rcu-lgm", "syscon";
+ reg = <0x000000 0x80000>;
+ intel,global-reset = <0x10 30>;
+ #reset-cells = <2>;
+ };
+
+ pcie_phy0: pciephy@... {
+ ...
+ /* address offset: 0x10, bit offset: 12 */
+ resets = <&rcu0 0x10 12>;
+ ...
+ };
--
2.11.0