Re: [PATCH v5 00/20] KVM RISC-V Support

[Alexander Graf]

On 23.08.19 14:19, Anup Patel wrote:
> On Fri, Aug 23, 2019 at 5:40 PM Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
> > On 23/08/19 13:44, Graf (AWS), Alexander wrote:
> > > > Overall, I'm quite happy with the code. It's a very clean implementation
> > > > of a KVM target.
> >
> > Yup, I said the same even for v1 (I prefer recursive implementation of
> > page table walking but that's all I can say).
> >
> > > > I will send v6 next week. I will try my best to implement unpriv
> > > > trap handling in v6 itself.
> > > Are you sure unpriv is the only exception that can hit there? What
> > > about NMIs? Do you have #MCs yet (ECC errors)? Do you have something
> > > like ARM's #SError which can asynchronously hit at any time because
> > > of external bus (PCI) errors?
> >
> > As far as I know, all interrupts on RISC-V are disabled by
> > local_irq_disable()/local_irq_enable().
>
> Yes, we don't have per-CPU interrupts for async bus errors or
> non-maskable interrupts. The local_irq_disable() and local_irq_enable()
> affect all interrupts (excepts traps).

Awesome, so that means you really only need to worry about traps. Even 
easier then! :)

Also, you want to look out for a future extension that adds any of the 
above (NMI, MCE, SError on local bus), as that would then break the 
function ;)


Alex