[PATCH 5.2 115/162] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks

[Greg Kroah-Hartman]

From: Dinh Nguyen <dinguyen@xxxxxxxxxx>

commit c7ec75ea4d5316518adc87224e3cff47192579e7 upstream.

Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.

Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@xxxxxxxxxx
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

---
 drivers/clk/socfpga/clk-periph-s10.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_re
 	if (socfpgaclk->fixed_div) {
 		div = socfpgaclk->fixed_div;
 	} else {
-		if (!socfpgaclk->bypass_reg)
+		if (socfpgaclk->hw.reg)
 			div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
 	}