Re: [Patch v3] drivers: mtd: spi-nor: Add flash property for mt25qu512a and mt35xu02g

[Tudor.Ambarus]

Hi, Ashish,

On 08/13/2019 01:38 PM, Ashish Kumar wrote:
> External E-Mail
> 
> 
> mt25qu512a is rebranded after its spinoff from STM, so it is
> different only in term of operating frequency, initial JEDEC id
> is same as that of n25q512a. In order to avoid any confussion
> with respect to name new entry is added.
> This flash is tested for Single I/O and QUAD I/O mode on LS1046FRWY.
> 
> mt35xu02g is Octal flash supporting Single I/O and QCTAL I/O
> and it has been tested on LS1028ARDB
> 
> Signed-off-by: Kuldeep Singh <kuldeep.singh@xxxxxxx>
> Signed-off-by: Ashish Kumar <ashish.kumar@xxxxxxx>
> ---
> v3:
> -Reword commits msg
> -rebase to top of mtd-linux spi-nor/next
> v2:
> Incorporate review comments from Vignesh
> 
>  drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 03cc788..97d3de8 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1988,6 +1988,12 @@ static const struct flash_info spi_nor_ids[] = {
>  	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
>  	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>  	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
> +
> +	/* Micron */
> +	{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024, SECT_4K |
> +				USE_FSR | SPI_NOR_DUAL_READ |
> +				SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },

I'm looking at the following datasheets: mt25qu512a [1] and n25q512a [2].
Both flashes have the same Extended Device ID data. What will happen, is that
you'll always hit the first valid entry, so "mt25qu512a", and you'll indicate a
'wrong' flash name for n25q512a. If there is nothing that differentiate between
the two, maybe you can add a comment in the code that says that "n25q512a" was
re-branded to "mt25qu512a" after the STM spin-off. Whatever solution will be, it
will be better if you do it in a separate patch.

[1]
https://static6.arrow.com/aropdfconversion/1a8b08cb08427821f166137d064c4837eca70f15/12682797700728481268266842945946mt25q_qlkt_u_512_abb_0.pdf.pdf

[2]
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=2ahUKEwjZlJ_M_KLkAhWB66QKHV6WAX4QFjAAegQIAhAC&url=https%3A%2F%2Fwww.micron.com%2F-%2Fmedia%2Fdocuments%2Fproducts%2Fdata-sheet%2Fnor-flash%2Fserial-nor%2Fn25q%2Fn25q_512mb_1_8v_65nm.pdf&usg=AOvVaw3BSiUIfTgikFZ0FZ7O_D61

> +
>  	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>  	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>  	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> @@ -2003,6 +2009,9 @@ static const struct flash_info spi_nor_ids[] = {
>  			SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
>  			SPI_NOR_4B_OPCODES)
>  	},
> +	{ "mt35xu02g",  INFO(0x2c5b1c, 0, 128 * 1024, 2048,
> +			SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
> +			SPI_NOR_4B_OPCODES) },

Is there a public datasheet for this flash?

Cheers,
ta