Re: [PATCH v2 3/6] powerpc: Convert flush_icache_range & friends to C

[Christophe Leroy]

Le 03/09/2019 Ã 15:04, Segher Boessenkool a ÃcritÂ:
> Hi!
>
> On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
> > diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
>
> > +#if !defined(CONFIG_PPC_8xx) & !defined(CONFIG_PPC64)
>
> Please write that as &&?  That is more usual, and thus, easier to read.
>
> > +static void flush_dcache_icache_phys(unsigned long physaddr)
>
> > +	asm volatile(
> > +		"   mtctr %2;"
> > +		"   mtmsr %3;"
> > +		"   isync;"
> > +		"0: dcbst   0, %0;"
> > +		"   addi    %0, %0, %4;"
> > +		"   bdnz    0b;"
> > +		"   sync;"
> > +		"   mtctr %2;"
> > +		"1: icbi    0, %1;"
> > +		"   addi    %1, %1, %4;"
> > +		"   bdnz    1b;"
> > +		"   sync;"
> > +		"   mtmsr %5;"
> > +		"   isync;"
> > +		: "+r" (loop1), "+r" (loop2)
> > +		: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
> > +		: "ctr", "memory");
>
> This outputs as one huge assembler statement, all on one line.  That's
> going to be fun to read or debug.

Do you mean \n has to be added after the ; ?

> loop1 and/or loop2 can be assigned the same register as msr0 or nb.  They
> need to be made earlyclobbers.  (msr is fine, all of its reads are before
> any writes to loop1 or loop2; and bytes is fine, it's not a register).

Can you explicit please ? Doesn't '+r' means that they are input and 
output at the same time ?

"to be made earlyclobbers", what does this means exactly ? How to do that ?

Christophe