Re: [PATCH] arm64: dts: imx8mq: Add CAAM node

[Horia Geanta]

On 8/31/2019 12:01 AM, Andrey Smirnov wrote:
> Add node for CAAM - Cryptographic Acceleration and Assurance Module.
> 
> Signed-off-by: Horia Geantă <horia.geanta@xxxxxxx>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> Cc: Cory Tusar <cory.tusar@xxxxxxxx>
> Cc: Chris Healy <cphealy@xxxxxxxxx>
> Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Cc: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: Iuliana Prodan <iuliana.prodan@xxxxxxx>
> Cc: linux-crypto@xxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> ---
> 
> Shawn:
> 
> Just a bit of a context: as per this thread
> https://lore.kernel.org/linux-crypto/20190830131547.GA27480@xxxxxxxxxxxxxxxxxxx/
> I am hoping I can get and Ack from you for this patch, so it can go
> via cryptodev tree.
> 
Could we please get an Ack in time for v5.4?

Thanks,
Horia

> Thanks,
> Andrey Smirnov
> 
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index d09b808eff87..752d5a61878c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -728,6 +728,36 @@
>  				status = "disabled";
>  			};
>  
> +			crypto: crypto@30900000 {
> +				compatible = "fsl,sec-v4.0";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x30900000 0x40000>;
> +				ranges = <0 0x30900000 0x40000>;
> +				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_AHB>,
> +					 <&clk IMX8MQ_CLK_IPG_ROOT>;
> +				clock-names = "aclk", "ipg";
> +
> +				sec_jr0: jr@1000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x1000 0x1000>;
> +					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr1: jr@2000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x2000 0x1000>;
> +					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr2: jr@3000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x3000 0x1000>;
> +					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +			};
> +
>  			i2c1: i2c@30a20000 {
>  				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
>  				reg = <0x30a20000 0x10000>;
>