[tip: irq/core] dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support

[tip-bot2 for Marc Zyngier]

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     4b049063e0bcbfd302f6bf867de9d55a965d622e
Gitweb:        https://git.kernel.org/tip/4b049063e0bcbfd302f6bf867de9d55a965d622e
Author:        Marc Zyngier <maz@xxxxxxxxxx>
AuthorDate:    Thu, 18 Jul 2019 13:18:51 +01:00
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Tue, 20 Aug 2019 10:23:35 +01:00

dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support

Update the GICv3 binding to allow interrupts in the EPPI range.

Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
---
 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index 98a3ecd..1fe147d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -44,12 +44,13 @@ properties:
       be at least 4.
 
       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
-      interrupts, 2 for interrupts in the Extended SPI range. Other values
-      are reserved for future use.
+      interrupts, 2 for interrupts in the Extended SPI range, 3 for the
+      Extended PPI range. Other values are reserved for future use.
 
       The 2nd cell contains the interrupt number for the interrupt type.
       SPI interrupts are in the range [0-987]. PPI interrupts are in the
       range [0-15]. Extented SPI interrupts are in the range [0-1023].
+      Extended PPI interrupts are in the range [0-127].
 
       The 3rd cell is the flags, encoded as follows:
       bits[3:0] trigger type and level flags.