Re: [PATCH v2 3/3] media: Add support for Cadence CSI2RX 2.1

[Jan Kotas]

Hello Sakari,

Thanks for the review.

> On 6 Sep 2019, at 10:01, Sakari Ailus <sakari.ailus@xxxxxx> wrote:
> 
> Hi Jan,
> 
> On Thu, Sep 05, 2019 at 11:56:01AM +0100, Jan Kotas wrote:
>> This patch adds support for CSI2RX v2.1 version of the controller.
>> 
>> Signed-off-by: Jan Kotas <jank@xxxxxxxxxxx>
>> ---
>> drivers/media/platform/cadence/cdns-csi2rx.c | 139 ++++++++++++++++++++++-----
>> 1 file changed, 116 insertions(+), 23 deletions(-)
>> 
>> struct csi2rx_priv {
>> 	struct device			*dev;
>> 	unsigned int			count;
>> @@ -69,6 +81,7 @@ struct csi2rx_priv {
>> 	struct clk			*p_clk;
>> 	struct clk			*pixel_clk[CSI2RX_STREAMS_MAX];
>> 	struct phy			*dphy;
>> +	struct csi2rx_vops		*vops;
> 
> const?

Iâll add it, thanks.

>> 
>> 	u8				lanes[CSI2RX_LANES_MAX];
>> 	u8				num_lanes;
>> @@ -92,6 +105,32 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev)
>> 	return container_of(subdev, struct csi2rx_priv, subdev);
>> }
>> 
>> +static void csi2rx_get_dev_cfg(struct csi2rx_priv *csi2rx)
>> +{
>> +	u32 dev_cfg;
>> +
>> +	clk_prepare_enable(csi2rx->p_clk);
>> +	dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG);
>> +	clk_disable_unprepare(csi2rx->p_clk);
>> +
>> +	csi2rx->max_lanes = dev_cfg & 7;
>> +	csi2rx->max_streams = (dev_cfg >> 4) & 7;
>> +	csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false;
> 
> Could you spell out these a little, by adding #defines for the register
> bits? Same below.

I tried to keep impact on the original code to the minimum, 
but youâre right. Itâs a good opportunity for a cleanup. 

>> 
>> @@ -439,6 +535,9 @@ static int csi2rx_probe(struct platform_device *pdev)
>> 	csi2rx->dev = &pdev->dev;
>> 	mutex_init(&csi2rx->lock);
>> 
>> +	of_id = of_match_node(csi2rx_of_table, pdev->dev.of_node);
>> +	csi2rx->vops = (struct csi2rx_vops *)of_id->data;
> 
> The cast isn't needed, is it?

Itâs not, but doesnât make it more readable?

> -- 
> Kind regards,
> 
> Sakari Ailus

Regards,
Jan