Quoting Lina Iyer (2019-09-03 10:07:22)Thanks for pointing to this.
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
>On 02/09/2019 14:38, Rob Herring wrote:
>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
These are not GIC registers but located on the PDC interface to the GIC.
They may or may not be secure access controlled, depending on the SoC.
It looks like it falls under this "mailbox" device which is really the
catch all bucket for bits with no home besides they're related to the
apps CPUs/subsystem.
apss_shared: mailbox@17990000 {But this doesn't seem correct. The registers in this page are all not
compatible = "qcom,sdm845-apss-shared";
reg = <0 0x17990000 0 0x1000>;
#mbox-cells = <1>;The register space collection seems to be mix of different types of
};
Can you point to this node with a phandle and then parse the reg
property out of it to use in the scm readl/writel APIs? Maybe it can be
a two cell property with <&apps_shared 0xf0> to indicate the offset to
the registers to read/write? In non-secure mode presumably we need to
also write these registers? Good news is that there's a regmap for this
driver already, so maybe that can be acquired from the pdc driver.