Re: [v7 1/2] mtd: rawnand: Add new Cadence NAND driver to MTD subsystem (fwd)

From: Miquel Raynal
Date: Wed Sep 25 2019 - 04:18:02 EST

Next message: Maarten Lankhorst: "Re: [PATCH 1/3] drm: Add some new format DRM_FORMAT_NVXX_10"
Previous message: Konstantin Khlebnikov: "Re: [PATCH v2] mm: implement write-behind policy for sequential file writes"
Next in thread: Piotr Sroka: "Re: [v7 1/2] mtd: rawnand: Add new Cadence NAND driver to MTD subsystem (fwd)"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi Piotr,

Can you fix the below issue reported by Julia? Either convert the
structure parameter to a signed parameter or use an intermediate
variable.

Thanks,
MiquÃl

Julia Lawall <julia.lawall@xxxxxxx> wrote on Wed, 18 Sep 2019 21:04:37
+0200 (CEST):

> ---------- Forwarded message ----------
> Date: Wed, 18 Sep 2019 23:17:29 +0800
> From: kbuild test robot <lkp@xxxxxxxxx>
> To: kbuild@xxxxxx
> Cc: Julia Lawall <julia.lawall@xxxxxxx>
> Subject: Re: [v7 1/2] mtd: rawnand: Add new Cadence NAND driver to MTD subsystem
>
> CC: kbuild-all@xxxxxx
> In-Reply-To: <20190918123115.30510-1-piotrs@xxxxxxxxxxx>
> References: <20190918123115.30510-1-piotrs@xxxxxxxxxxx>
> TO: Piotr Sroka <piotrs@xxxxxxxxxxx>
> CC: Kazuhiro Kasai <kasai.kazuhiro@xxxxxxxxxxxxx>, Piotr Sroka <piotrs@xxxxxxxxxxx>, Miquel Raynal <miquel.raynal@xxxxxxxxxxx>, Richard Weinberger <richard@xxxxxx>, David Woodhouse <dwmw2@xxxxxxxxxxxxx>, Brian Norris <computersforpeace@xxxxxxxxx>, Marek Vasut <marek.vasut@xxxxxxxxx>, Vignesh Raghavendra <vigneshr@xxxxxx>, Mauro Carvalho Chehab <mchehab+samsung@xxxxxxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>, Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Linus Walleij <linus.walleij@xxxxxxxxxx>, Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>, "Paul E. McKenney" <paulmck@xxxxxxxxxxxxx>, Boris Brezillon <boris.brezillon@xxxxxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, Paul Cercueil <paul@xxxxxxxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>, Liang Yang <liang.yang@xxxxxxxxxxx>, Anders Roxell <anders.roxell@xxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, linux-mtd@xxxxxxxxxxxxxxxxxxx
>
> Hi Piotr,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on linus/master]
> [cannot apply to v5.3 next-20190917]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Piotr-Sroka/mtd-rawnand-Add-new-Cadence-NAND-driver-to-MTD-subsystem/20190918-204505
> :::::: branch date: 3 hours ago
> :::::: commit date: 3 hours ago
>
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@xxxxxxxxx>
> Reported-by: Julia Lawall <julia.lawall@xxxxxxx>
>
> >> drivers/mtd/nand/raw/cadence-nand-controller.c:2644:5-28: WARNING: Unsigned expression compared with zero: cdns_chip -> corr_str_idx < 0
>
> # https://github.com/0day-ci/linux/commit/3235ae79d58b8d95b44d5d3773f59065f04d4f00
> git remote add linux-review https://github.com/0day-ci/linux
> git remote update linux-review
> git checkout 3235ae79d58b8d95b44d5d3773f59065f04d4f00
> vim +2644 drivers/mtd/nand/raw/cadence-nand-controller.c
>
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2584
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2585 int cadence_nand_attach_chip(struct nand_chip *chip)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2586 {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2587 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2588 struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2589 u32 ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2590 struct mtd_info *mtd = nand_to_mtd(chip);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2591 u32 max_oob_data_size;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2592 int ret;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2593
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2594 if (chip->options & NAND_BUSWIDTH_16) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2595 ret = cadence_nand_set_access_width16(cdns_ctrl, true);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2596 if (ret)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2597 goto free_buf;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2598 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2599
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2600 chip->bbt_options |= NAND_BBT_USE_FLASH;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2601 chip->bbt_options |= NAND_BBT_NO_OOB;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2602 chip->ecc.mode = NAND_ECC_HW;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2603
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2604 chip->options |= NAND_NO_SUBPAGE_WRITE;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2605
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2606 cdns_chip->bbm_offs = chip->badblockpos;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2607 if (chip->options & NAND_BUSWIDTH_16) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2608 cdns_chip->bbm_offs &= ~0x01;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2609 cdns_chip->bbm_len = 2;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2610 } else {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2611 cdns_chip->bbm_len = 1;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2612 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2613
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2614 ret = nand_ecc_choose_conf(chip,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2615 &cdns_ctrl->ecc_caps,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2616 mtd->oobsize - cdns_chip->bbm_len);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2617 if (ret) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2618 dev_err(cdns_ctrl->dev, "ECC configuration failed\n");
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2619 goto free_buf;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2620 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2621
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2622 dev_dbg(cdns_ctrl->dev,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2623 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2624 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2625
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2626 /* Error correction configuration. */
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2627 cdns_chip->sector_size = chip->ecc.size;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2628 cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2629
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2630 cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2631
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2632 max_oob_data_size = MAX_OOB_SIZE_PER_SECTOR;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2633
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2634 if (cdns_chip->avail_oob_size > max_oob_data_size)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2635 cdns_chip->avail_oob_size = max_oob_data_size;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2636
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2637 if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2638 > mtd->oobsize)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2639 cdns_chip->avail_oob_size -= 4;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2640
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2641 cdns_chip->corr_str_idx =
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2642 cadence_nand_get_ecc_strength_idx(cdns_ctrl,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2643 chip->ecc.strength);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 @2644 if (cdns_chip->corr_str_idx < 0)
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2645 return -EINVAL;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2646
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2647 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2648 1000000,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2649 CTRL_STATUS_CTRL_BUSY, true))
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2650 return -ETIMEDOUT;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2651
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2652 cadence_nand_set_ecc_strength(cdns_ctrl,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2653 cdns_chip->corr_str_idx);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2654
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2655 cadence_nand_set_erase_detection(cdns_ctrl, true,
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2656 chip->ecc.strength);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2657
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2658 /* Override the default read operations. */
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2659 chip->ecc.read_page = cadence_nand_read_page;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2660 chip->ecc.read_page_raw = cadence_nand_read_page_raw;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2661 chip->ecc.write_page = cadence_nand_write_page;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2662 chip->ecc.write_page_raw = cadence_nand_write_page_raw;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2663 chip->ecc.read_oob = cadence_nand_read_oob;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2664 chip->ecc.write_oob = cadence_nand_write_oob;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2665 chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2666 chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2667
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2668 if ((mtd->writesize + mtd->oobsize) > cdns_ctrl->buf_size) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2669 cdns_ctrl->buf_size = mtd->writesize + mtd->oobsize;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2670 kfree(cdns_ctrl->buf);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2671 cdns_ctrl->buf = kzalloc(cdns_ctrl->buf_size, GFP_KERNEL);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2672 if (!cdns_ctrl->buf) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2673 ret = -ENOMEM;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2674 goto free_buf;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2675 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2676 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2677
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2678 /* Is 32-bit DMA supported? */
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2679 ret = dma_set_mask(cdns_ctrl->dev, DMA_BIT_MASK(32));
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2680 if (ret) {
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2681 dev_err(cdns_ctrl->dev, "no usable DMA configuration\n");
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2682 goto free_buf;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2683 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2684
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2685 mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2686
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2687 return 0;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2688
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2689 free_buf:
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2690 kfree(cdns_ctrl->buf);
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2691
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2692 return ret;
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2693 }
> 3235ae79d58b8d Piotr Sroka 2019-09-18 2694
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation

Next message: Maarten Lankhorst: "Re: [PATCH 1/3] drm: Add some new format DRM_FORMAT_NVXX_10"
Previous message: Konstantin Khlebnikov: "Re: [PATCH v2] mm: implement write-behind policy for sequential file writes"
Next in thread: Piotr Sroka: "Re: [v7 1/2] mtd: rawnand: Add new Cadence NAND driver to MTD subsystem (fwd)"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]