Re: [PATCH v1 0/2] spi: cadence-qspi: Add cadence-qspi support for Intel LGM SoC

[Ramuthevar, Vadivel MuruganX]

Hi Vignesh,

On 10/10/2019 12:18 PM, Vignesh Raghavendra wrote:
> On 10/10/19 7:04 AM, Ramuthevar, Vadivel MuruganX wrote:
> > HI Vignesh,
> >
> > On 17/9/2019 12:50 AM, Vignesh Raghavendra wrote:
> > > Hi,
> > >
> > > On 16/09/19 1:08 PM, Ramuthevar,Vadivel MuruganX wrote:
> > > > patch 1: Add YAML for cadence-qspi devicetree cdocumentation.
> > > > patch 2: cadence-qspi controller driver to support QSPI-NAND flash
> > > > using existing spi-nand framework with legacy spi protocol.
> > > Nope, you cannot have two drivers for the same IP (i.e Cadence QSPI)
> > > just to support to different types of SPI memories. This is the reason
> > > why spi_mem_ops was introduced.
> > >
> > > Please rewrite this driver over to use spi_mem_ops (instead of using
> > > generic SPI xfers) so that same driver supports both SPI-NOR and
> > > SPI-NAND flashes. Once that's done drivers/mtd/spi-nor/cadence-quadspi.c
> > > can be deleted.
> > >
> > > There are few existing examples of spi_mem_ops users in drivers/spi/
> > > (git grep spi_mem_ops) and materials here on how to write such a driver:
> > >
> > > [1]
> > > https://bootlin.com/blog/spi-mem-bringing-some-consistency-to-the-spi-memory-ecosystem/
> > >
> > > [2] https://www.youtube.com/watch?v=PkWbuLM_gmU
> > As per Mark Brown and your suggestion, I have started adapting
> > cadence-qaudspi driver with spi_mem_ops framework to work
> > QSPI-NAND/NOR as a generic driver(completely removed the legacy
> > SPI-XFERS), is in progress on Intel LGM SoC.
> > QSPI-IP on Intel LGMÂ do not have DMAÂ support and also not part of QSPI
> > IP, so couldn't able to validate DMA related.
> > will adapt the DMA things which are existing in cadence-quadspi.c as it is.
> Great, appreciate the effort!
>
> > currently TI and Altera SoC's use this Cadence-qspi IP , both are not
> > using DMA as per my understanding (correct me if it is wrong).
> > confirmed through device tree entry.
> TI platforms use DMA to read data from flash in memory mapped mode
> (direct access controller) using mem-to-mem DMA channels. Mem-to-mem DMA
> channels are requested as and when needed and are not part of DT
> description (as they are not bound to a device)
yes, understood now, Thanks!
> > what is your opinion on DMA related stuff?
> Not having DMA support would be a regression. Please keep the DAC + DMA
> part as is. I can help you will all the DMA related testing...
Sure, will keep DAC + DMA, as we discussed earlier use QUIRKS to 
differentiate and follow the same.

---
With Regards
Vadivel

> Regards
> Vignesh
>
> > also using macronix(QSPI-NOR)
> > flash/Micron(QSPI-NAND).
> > ---
> > With Regards
> > Vadivel
> > > > Ramuthevar Vadivel Murugan (2):
> > > >  ÂÂ dt-bindings: spi: Add support for cadence-qspi IP Intel LGM SoC
> > > >  ÂÂ spi: cadence-qspi: Add QSPI support for Intel LGM SoC
> > > >
> > > >  Â .../devicetree/bindings/spi/cadence,qspi-nand.yaml |Â 84 +++
> > > >  Â drivers/spi/KconfigÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |ÂÂ 9 +
> > > >  Â drivers/spi/MakefileÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |ÂÂ 1 +
> > > >  Â drivers/spi/spi-cadence-qspi-apb.cÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ | 644
> > > > +++++++++++++++++++++
> > > >  Â drivers/spi/spi-cadence-qspi-apb.hÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ | 174 ++++++
> > > >  Â drivers/spi/spi-cadence-qspi.cÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ | 461
> > > > +++++++++++++++
> > > >  Â drivers/spi/spi-cadence-qspi.hÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |Â 73 +++
> > > >  Â 7 files changed, 1446 insertions(+)
> > > >  Â create mode 100644
> > > > Documentation/devicetree/bindings/spi/cadence,qspi-nand.yaml
> > > >  Â create mode 100644 drivers/spi/spi-cadence-qspi-apb.c
> > > >  Â create mode 100644 drivers/spi/spi-cadence-qspi-apb.h
> > > >  Â create mode 100644 drivers/spi/spi-cadence-qspi.c
> > > >  Â create mode 100644 drivers/spi/spi-cadence-qspi.h