On Thu, Oct 10, 2019 at 12:41:11PM +0200, Manfred Spraul wrote:
Hi,Yep. Either the atomic instruction implies ordering (eg. x86 LOCK
Waiman Long noticed that the memory barriers in sem_lock() are not really
documented, and while adding documentation, I ended up with one case where
I'm not certain about the wake_q code:
Questions:
- Does smp_mb__before_atomic() + a (failed) cmpxchg_relaxed provide an
 ordering guarantee?
prefix) or it doesn't (most RISC LL/SC), if it does,
smp_mb__{before,after}_atomic() are a NO-OP and the ordering is
unconditinoal, if it does not, then smp_mb__{before,after}_atomic() are
unconditional barriers.
- Is it ok that wake_up_q just writes wake_q->next, shouldn'tThere is no such thing as store_acquire, it is either load_acquire or
 smp_store_acquire() be used? I.e.: guarantee that wake_up_process()
 happens after cmpxchg_relaxed(), assuming that a failed cmpxchg_relaxed
 provides any ordering.
store_release. But just like how we can write load-aquire like
load+smp_mb(), so too I suppose we could write store-acquire like
store+smp_mb(), and that is exactly what is there (through the implied
barrier of wake_up_process()).
rewritten:Your example is incomplete (there is no A=1 assignment for example), but
start condition: A = 1; B = 0;
CPU1:
ÂÂÂ B = 1;
ÂÂÂ RELEASE, unlock LockX;
CPU2:
ÂÂÂ lock LockX, ACQUIRE
ÂÂÂ if (LOAD A == 1) return; /* using cmp_xchg_relaxed */
CPU2:
ÂÂÂ A = 0;
ÂÂÂ ACQUIRE, lock LockY
ÂÂÂ smp_mb__after_spinlock();
ÂÂÂ READ B
Question: is A = 1, B = 0 possible?
I'm thinking I can guess where that should go given the earlier text.
I don't think this is broken.