Re: [PATCH] MIPS: add support for SGI Octane (IP30)

[Joshua Kinard]

On 10/9/2019 14:43, Christoph Hellwig wrote:
>> +++ b/arch/mips/sgi-ip30/ip30-pci.c
>> @@ -0,0 +1,19 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * ip30-pci.c: misc PCI related helper code for IP30 architecture
>> + */
>> +
>> +#include <asm/pci/bridge.h>
>> +
>> +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
>> +{
>> +	struct pci_dev *pdev = to_pci_dev(dev);
>> +	struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
>> +
>> +	return bc->baddr + paddr;
>> +}
>> +
>> +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
>> +{
>> +	return dma_addr & ~(0xffUL << 56);
>> +}
> 
> This file is duplicated from ip27.  I think we should aim to share
> it given the common hardware even if it is mostly trivial.
> 

It's possible that we may need to add an IP30-specific WAR here eventually.
 OpenBSD code has this to say about BRIDGE on IP30 systems:

http://bxr.su/OpenBSD/sys/arch/sgi/sgi/ip30_machdep.c

144    /*
145     * Register DMA-reachable memory constraints.
146     * The xbridge(4) is limited to a 31-bit region (its IOMMU features
147     * are too restricted to be of use).
148     */
149    dma_constraint.ucr_low = 0;
150    dma_constraint.ucr_high = (1UL << 31) - 1;

I never figured out how in Linux one does something equivalent.  I knew it
needed to be done in the older dma-coherence.h file, and now in the newer
__phys_to_dma() function here.  This is, if memory recalls correctly,
because >2GB RAM in Octane causes issues w/ BRIDGE DMA access.

OpenBSD applies this same limit to IP27, but I have a sneaking suspicion
that it's strictly an IP30 hardware bug, because my Onyx2 has 8GB of RAM and
it usually boots fine on its own.  Pop more than 2GB into an Octane, though,
and, if it boots at all, disk or network I/O will usually bus error it at
some point.

-- 
Joshua Kinard
Gentoo/MIPS
kumba@xxxxxxxxxx
rsa6144/5C63F4E3F5C6C943 2015-04-27
177C 1972 1FB8 F254 BAD0 3E72 5C63 F4E3 F5C6 C943

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