[PATCH 0/6] V2: Clarify/standardize memory barriers for ipc
From: Manfred Spraul
Date: Sat Oct 12 2019 - 01:50:29 EST
Hi,
Updated series, based on input from Davidlohr:
- Mixing WRITE_ONCE(), when not holding a lock, and "normal" writes,
when holding a lock, makes the code less readable.
Thus use _ONCE() everywhere, for both WRITE_ONCE() and READ_ONCE().
- According to my understanding, wake_q_add() does not contain a barrier
that protects the refount increase. Document that, and add the barrier
to the ipc code
- and, based on patch review: The V1 patch for ipc/sem.c is incorrect,
->state must be set to "-EINTR", not EINTR.
>From V1:
The memory barriers in ipc are not properly documented, and at least
for some architectures insufficient:
Reading the xyz->status is only a control barrier, thus
smp_acquire__after_ctrl_dep() was missing in mqueue.c and msg.c
sem.c contained a full smp_mb(), which is not required.
Patches:
Patch 1: Document the barrier rules for wake_q_add().
Patch 2: remove code duplication
@Davidlohr: There is no "Signed-off-by" in your mail, otherwise I would
list you as author.
Patch 3-5: Update the ipc code, especially add missing
smp_mb__after_ctrl_dep().
Clarify that smp_mb__{before,after}_atomic() are compatible with all
RMW atomic operations, not just the operations that do not return a value.
Patch 6: Documentation for smp_mb__{before,after}_atomic().
Open issues:
- Is my analysis regarding the refcount correct?
- Review other users of wake_q_add().
- More testing. I did some tests, but doubt that the tests would be
sufficient to show issues with regards to incorrect memory barriers.
- Should I add a "Fixes:" or "Cc:stable"? The issues that I see are
the missing smp_mb__after_ctrl_dep(), and WRITE_ONCE() vs.
"ptr = NULL", and a risk regarding the refcount that I can't evaluate.
What do you think?
--
Manfred