On 10/15/2019 09:40 AM, Xiaoyao Li wrote:
Move the MSR bitmap setup codes to vmx_vmcs_setup() and only setup them
when hardware has msr_bitmap capability.
Signed-off-by: Xiaoyao Li <xiaoyao.li@xxxxxxxxx>
---
 arch/x86/kvm/vmx/vmx.c | 39 ++++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 58b77a882426..7051511c27c2 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -4164,12 +4164,30 @@ static void ept_set_mmio_spte_mask(void)
 static void vmx_vmcs_setup(struct vcpu_vmx *vmx)
 {
ÂÂÂÂÂ int i;
+ÂÂÂ unsigned long *msr_bitmap;
ÂÂÂÂÂ if (nested)
ÂÂÂÂÂÂÂÂÂ nested_vmx_vmcs_setup();
-ÂÂÂ if (cpu_has_vmx_msr_bitmap())
-ÂÂÂÂÂÂÂ vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
+ÂÂÂ if (cpu_has_vmx_msr_bitmap()) {
+ÂÂÂÂÂÂÂ msr_bitmap = vmx->vmcs01.msr_bitmap;
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
vmx_disable_intercept_for_msr() also calls cpu_has_vmx_msr_bitmap(), which means we are repeating the check. A cleaner approach is to remove the call to cpu_has_vmx_msr_bitmap()Â from vmx_disable_intercept_for_msr()Â and let its callers do the check just like you are doing here.
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
+ÂÂÂÂÂÂÂ if (kvm_cstate_in_guest(vmx->vcpu.kvm)) {
+ÂÂÂÂÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
+ÂÂÂÂÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
+ÂÂÂÂÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
+ÂÂÂÂÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
+ÂÂÂÂÂÂÂ }
+
+ÂÂÂÂÂÂÂ vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
+ÂÂÂ }
+ÂÂÂ vmx->msr_bitmap_mode = 0;
ÂÂÂÂÂ vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
@@ -6697,7 +6715,6 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
 {
ÂÂÂÂÂ int err;
ÂÂÂÂÂ struct vcpu_vmx *vmx;
-ÂÂÂ unsigned long *msr_bitmap;
ÂÂÂÂÂ int cpu;
ÂÂÂÂÂ BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
@@ -6754,22 +6771,6 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
ÂÂÂÂÂ if (err < 0)
ÂÂÂÂÂÂÂÂÂ goto free_msrs;
-ÂÂÂ msr_bitmap = vmx->vmcs01.msr_bitmap;
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
-ÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
-ÂÂÂ if (kvm_cstate_in_guest(kvm)) {
-ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
-ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
-ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
-ÂÂÂÂÂÂÂ vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
-ÂÂÂ }
-ÂÂÂ vmx->msr_bitmap_mode = 0;
-
ÂÂÂÂÂ vmx->loaded_vmcs = &vmx->vmcs01;
ÂÂÂÂÂ cpu = get_cpu();
ÂÂÂÂÂ vmx_vcpu_load(&vmx->vcpu, cpu);