[GIT PULL] RISC-V updates for v5.4-rc4

[Paul Walmsley]

Linus,

The following changes since commit 4f5cafb5cb8471e54afdc9054d973535614f7675:

  Linux 5.4-rc3 (2019-10-13 16:37:36 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.4-rc4

for you to fetch changes up to 5bf4e52ff0317db083fafee010dc806f8d4cb0cb:

  RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START (2019-10-15 22:47:41 -0700)

----------------------------------------------------------------
RISC-V updates for v5.4-rc4

Some RISC-V fixes for v5.4-rc4:

- Fix the virtual memory layout so the fixaddr region doesn't overlap
  with other regions.  (This was originally intended to go in as part
  of an earlier patch, but I inadvertently dropped it during a
  rebase.)

- Add the DT chosen/stdout-path property to the HiFive Unleashed DT
  file.  This is so "earlycon" can be specified with no arguments on
  the kernel command line, and the correct UART will be automatically
  selected.

And two cleanup patches:

- Simplify the code in our breakpoint trap handler.

- Drop a comment in our TLB flush code that has caused some confusion.

----------------------------------------------------------------
Greentime Hu (1):
      RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START

Paul Walmsley (2):
      riscv: dts: HiFive Unleashed: add default chosen/stdout-path
      riscv: tlbflush: remove confusing comment on local_flush_tlb_all()

Vincent Chen (1):
      riscv: remove the switch statement in do_trap_break()

 .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts |  1 +
 arch/riscv/include/asm/pgtable.h                   | 16 ++++++++--------
 arch/riscv/include/asm/tlbflush.h                  |  4 ----
 arch/riscv/kernel/traps.c                          | 22 +++++++++++-----------
 4 files changed, 20 insertions(+), 23 deletions(-)