Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ

From: Alexander Sverdlin
Date: Sat Oct 19 2019 - 17:14:25 EST

Hi!

On Sat, 19 Oct 2019 22:44:18 +0200
Arnd Bergmann <arnd@xxxxxxxx> wrote:

> > > > # cat /proc/interrupts
> > > > CPU0
> > > > 39: 146 VIC 7 Edge eth0
> > > > 51: 162161 VIC 19 Edge ep93xx timer
> > > > 52: 139 VIC 20 Edge uart-pl010
> > > > 53: 4 VIC 21 Edge ep93xx-spi
> > > > 60: 0 VIC 28 Edge ep93xx-i2s
> > > > Err: 0
> > >
> > > I guess that is partial success: some irqs do work ;-)
> >
> > Yep, VIC1 is working, while VIC0 is not.
> >
> > > The two interrupts that did not get registered are for the
> > > dmaengine driver, and that makes sense given the error
> > > message about the DMA not working. No idea how
> > > that would be a result of the irq changes though.
> >
> > Seems, that it has exposed some incompatibilities of
> > starting IRQ 0 in EP93xx platform fir VIC0 and VIC code
> > itself, which assumes 0 means "auto assignment" (refer
> > to vic_init()).
>
> Ah, that makes sense. so all interrupt numbers need to
> be shifted by a fixed number (e.g. 1) like we did for
> other platforms (see attachment).

Yes, the below patch resolved both GPIO and DMA issues.
Previous patch (selecting IRQ_DOMAIN_HIERARCHY) is not
required.

If you re-spin all 3 ep93xx-relevant patches together, you can put my
Tested-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
on them.

> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 6fb19a393fd2..f0a71d4e076f 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -47,6 +47,7 @@
> #include <asm/mach/map.h>
>
> #include "soc.h"
> +#include "irqs.h"
>
> /*************************************************************************
> * Static I/O mappings that are needed for all EP93xx platforms
> @@ -75,8 +76,8 @@ void __init ep93xx_map_io(void)
> *************************************************************************/
> void __init ep93xx_init_irq(void)
> {
> - vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
> - vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
> + vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
> + vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0);
> }
>
>
> diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h
> index 3ffdb3a2f3e4..353201b90c66 100644
> --- a/arch/arm/mach-ep93xx/irqs.h
> +++ b/arch/arm/mach-ep93xx/irqs.h
> @@ -2,69 +2,73 @@
> #ifndef __ASM_ARCH_IRQS_H
> #define __ASM_ARCH_IRQS_H
>
> -#define IRQ_EP93XX_COMMRX 2
> -#define IRQ_EP93XX_COMMTX 3
> -#define IRQ_EP93XX_TIMER1 4
> -#define IRQ_EP93XX_TIMER2 5
> -#define IRQ_EP93XX_AACINTR 6
> -#define IRQ_EP93XX_DMAM2P0 7
> -#define IRQ_EP93XX_DMAM2P1 8
> -#define IRQ_EP93XX_DMAM2P2 9
> -#define IRQ_EP93XX_DMAM2P3 10
> -#define IRQ_EP93XX_DMAM2P4 11
> -#define IRQ_EP93XX_DMAM2P5 12
> -#define IRQ_EP93XX_DMAM2P6 13
> -#define IRQ_EP93XX_DMAM2P7 14
> -#define IRQ_EP93XX_DMAM2P8 15
> -#define IRQ_EP93XX_DMAM2P9 16
> -#define IRQ_EP93XX_DMAM2M0 17
> -#define IRQ_EP93XX_DMAM2M1 18
> -#define IRQ_EP93XX_GPIO0MUX 19
> -#define IRQ_EP93XX_GPIO1MUX 20
> -#define IRQ_EP93XX_GPIO2MUX 21
> -#define IRQ_EP93XX_GPIO3MUX 22
> -#define IRQ_EP93XX_UART1RX 23
> -#define IRQ_EP93XX_UART1TX 24
> -#define IRQ_EP93XX_UART2RX 25
> -#define IRQ_EP93XX_UART2TX 26
> -#define IRQ_EP93XX_UART3RX 27
> -#define IRQ_EP93XX_UART3TX 28
> -#define IRQ_EP93XX_KEY 29
> -#define IRQ_EP93XX_TOUCH 30
> +#define IRQ_EP93XX_VIC0 1
> +
> +#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2)
> +#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3)
> +#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4)
> +#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5)
> +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
> +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
> +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
> +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
> +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
> +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
> +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
> +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
> +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
> +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
> +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
> +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
> +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
> +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
> +#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20)
> +#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21)
> +#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22)
> +#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23)
> +#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24)
> +#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25)
> +#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26)
> +#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27)
> +#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28)
> +#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29)
> +#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30)
> #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
>
> -#define IRQ_EP93XX_EXT0 32
> -#define IRQ_EP93XX_EXT1 33
> -#define IRQ_EP93XX_EXT2 34
> -#define IRQ_EP93XX_64HZ 35
> -#define IRQ_EP93XX_WATCHDOG 36
> -#define IRQ_EP93XX_RTC 37
> -#define IRQ_EP93XX_IRDA 38
> -#define IRQ_EP93XX_ETHERNET 39
> -#define IRQ_EP93XX_EXT3 40
> -#define IRQ_EP93XX_PROG 41
> -#define IRQ_EP93XX_1HZ 42
> -#define IRQ_EP93XX_VSYNC 43
> -#define IRQ_EP93XX_VIDEO_FIFO 44
> -#define IRQ_EP93XX_SSP1RX 45
> -#define IRQ_EP93XX_SSP1TX 46
> -#define IRQ_EP93XX_GPIO4MUX 47
> -#define IRQ_EP93XX_GPIO5MUX 48
> -#define IRQ_EP93XX_GPIO6MUX 49
> -#define IRQ_EP93XX_GPIO7MUX 50
> -#define IRQ_EP93XX_TIMER3 51
> -#define IRQ_EP93XX_UART1 52
> -#define IRQ_EP93XX_SSP 53
> -#define IRQ_EP93XX_UART2 54
> -#define IRQ_EP93XX_UART3 55
> -#define IRQ_EP93XX_USB 56
> -#define IRQ_EP93XX_ETHERNET_PME 57
> -#define IRQ_EP93XX_DSP 58
> -#define IRQ_EP93XX_GPIO_AB 59
> -#define IRQ_EP93XX_SAI 60
> +#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32)
> +
> +#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0)
> +#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1)
> +#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2)
> +#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3)
> +#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4)
> +#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5)
> +#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6)
> +#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7)
> +#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8)
> +#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9)
> +#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10)
> +#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11)
> +#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12)
> +#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13)
> +#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14)
> +#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15)
> +#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16)
> +#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17)
> +#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18)
> +#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19)
> +#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20)
> +#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21)
> +#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22)
> +#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23)
> +#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24)
> +#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25)
> +#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26)
> +#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27)
> +#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28)
> #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
>
> -#define NR_EP93XX_IRQS (64 + 24)
> +#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24)
>
> #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
> #define EP93XX_BOARD_IRQS 32

--
Alexander Sverdlin.