On 2019-10-18 02:18, Srinivas Kandagatla wrote:Looks like copy paste error.. no reason for this to be here!!
+static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kc,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ÂÂÂ struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
+ÂÂÂ struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ wcd934x_codec_enable_int_port(dai, comp);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case SNDRV_PCM_TRIGGER_STOP:
+ÂÂÂÂÂÂÂ break;
Any reason for mentioning _TRIGGER_STOP here?
I could probably move this to hw_free callback.
+ÂÂÂ case SND_SOC_DAPM_POST_PMD:
+ÂÂÂÂÂÂÂ kfree(dai->sconfig.chs);
+
+ÂÂÂÂÂÂÂ break;
Comment for kfree depending on _event_ would be advised.
we could do that too! I will try to clean this bit up in next version.+ÂÂÂ }
+
+ÂÂÂ return 0;
+}
+
+static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u16 interp_idx, int event)
+{
+ÂÂÂ u16 hd2_scale_reg;
+ÂÂÂ u16 hd2_enable_reg = 0;
+
+ÂÂÂ switch (interp_idx) {
+ÂÂÂ case INTERP_HPHL:
+ÂÂÂÂÂÂÂ hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
+ÂÂÂÂÂÂÂ hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case INTERP_HPHR:
+ÂÂÂÂÂÂÂ hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
+ÂÂÂÂÂÂÂ hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ }
What's the rest of this function for if switch-case does not match?
Without hd2_enable_reg > 0 you might as well return immediately.
+
+ÂÂÂ if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(component, hd2_scale_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(component, hd2_enable_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
+ÂÂÂ }
+
+ÂÂÂ if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(component, hd2_enable_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(component, hd2_scale_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
+ÂÂÂ }
+}
+
+static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u16 interp_idx, int event)
+{
+ÂÂÂ u8 hph_dly_mask;
+ÂÂÂ u16 hph_lut_bypass_reg = 0;
+ÂÂÂ u16 hph_comp_ctrl7 = 0;
+
+ÂÂÂ switch (interp_idx) {
+ÂÂÂ case INTERP_HPHL:
+ÂÂÂÂÂÂÂ hph_dly_mask = 1;
+ÂÂÂÂÂÂÂ hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
+ÂÂÂÂÂÂÂ hph_comp_ctrl7 = WCD934X_CDC_COMPANDER1_CTL7;
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case INTERP_HPHR:
+ÂÂÂÂÂÂÂ hph_dly_mask = 2;
+ÂÂÂÂÂÂÂ hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
+ÂÂÂÂÂÂÂ hph_comp_ctrl7 = WCD934X_CDC_COMPANDER2_CTL7;
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ default:
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ }
'Default' made it here, what was not the case for most of other switch-case. Keep code consistent would be appreciated.
Moreover, in the following function "wcd934x_config_compander", you do decide to do all the processing directly within switch-case. I see no reason why you should not do that here too.
Again, once switch-case fails to find match, the rest of function does not do much, really.
+
+ÂÂÂ if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ hph_dly_mask, 0x0);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_LUT_BYPASS_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_LUT_BYPASS_ENABLE);
+ÂÂÂ }
+
+ÂÂÂ if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ hph_dly_mask, hph_dly_mask);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_LUT_BYPASS_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_LUT_BYPASS_DISABLE);
+ÂÂÂ }
+}
+
+static int wcd934x_config_compander(struct snd_soc_component *comp,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int interp_n, int event)
+{
+ÂÂÂ struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
+ÂÂÂ int compander;
+ÂÂÂ u16 comp_ctl0_reg, rx_path_cfg0_reg;
+
+ÂÂÂ /* EAR does not have compander */
+ÂÂÂ if (!interp_n)
+ÂÂÂÂÂÂÂ return 0;
+
+ÂÂÂ compander = interp_n - 1;
+ÂÂÂ if (!wcd->comp_enabled[compander])
+ÂÂÂÂÂÂÂ return 0;
+
+ÂÂÂ comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
+ÂÂÂ rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_PRE_PMU:
+ÂÂÂÂÂÂÂ /* Enable Compander Clock */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_CLK_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_CLK_ENABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_ENABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_DISABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_CMP_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_CMP_ENABLE);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case SND_SOC_DAPM_POST_PMD:
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_CMP_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_CMP_DISABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_HALT_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_HALT);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_ENABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_DISABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_CLK_EN_MASK, 0x0);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, comp_ctl0_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_COMP_SOFT_RST_MASK, 0x0);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ }
+
+ÂÂÂ return 0;
+}
+
+static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kc, int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ÂÂÂ int offset_val = 0;
+ÂÂÂ u16 gain_reg, mix_reg;
+ÂÂÂ int val = 0;
+
+ÂÂÂ gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
+ÂÂÂ mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_PRE_PMU:
+ÂÂÂÂÂÂÂ /* Clk enable */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, mix_reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_MIX_CLK_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_MIX_CLK_ENABLE);
+ÂÂÂÂÂÂÂ break;
+
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ val = snd_soc_component_read32(comp, gain_reg);
+ÂÂÂÂÂÂÂ val += offset_val;
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, gain_reg, val);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case SND_SOC_DAPM_POST_PMD:
+ÂÂÂÂÂÂÂ break;
Redundant case?.
+ÂÂÂ };
+
+ÂÂÂ return 0;
+}
+
+static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kcontrol, int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ÂÂÂ int reg = w->reg;
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ /* B1 GAIN */
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ snd_soc_component_read32(comp, reg));
+ÂÂÂÂÂÂÂ /* B2 GAIN */
+ÂÂÂÂÂÂÂ reg++;
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ snd_soc_component_read32(comp, reg));
+ÂÂÂÂÂÂÂ /* B3 GAIN */
+ÂÂÂÂÂÂÂ reg++;
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ snd_soc_component_read32(comp, reg));
+ÂÂÂÂÂÂÂ /* B4 GAIN */
+ÂÂÂÂÂÂÂ reg++;
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ snd_soc_component_read32(comp, reg));
+ÂÂÂÂÂÂÂ /* B5 GAIN */
+ÂÂÂÂÂÂÂ reg++;
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, reg,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ snd_soc_component_read32(comp, reg));
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ default:
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ }
+ÂÂÂ return 0;
Missing newline before return - based on format of your other functions.
+}
+
+static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kcontrol,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ÂÂÂ u16 gain_reg;hd2_
+ÂÂÂ u32 val;
+
+ÂÂÂ gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_CTL_OFFSET);
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ val = snd_soc_component_read32(comp, gain_reg);
+ÂÂÂÂÂÂÂ snd_soc_component_write(comp, gain_reg, val);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ };
In the function above, "wcd934x_codec_set_iir_gain", you decided against declaring local 'val' for storing _read32, though here, only for a single use-case, you made a difference. Let's keep it consistent and run with one or the other.
Also, is there any value for assigning gain_reg outside of switch-case?
+
+ÂÂÂ return 0;
+}
+static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kcontrol,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+
+ÂÂÂ switch (event) {hd2_
+ÂÂÂ case SND_SOC_DAPM_PRE_PMU:
+ÂÂÂÂÂÂÂ break;
Redundant case.
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ /*
+ÂÂÂÂÂÂÂÂ * 7ms sleep is required after PA is enabled as per
+ÂÂÂÂÂÂÂÂ * HW requirement. If compander is disabled, then
+ÂÂÂÂÂÂÂÂ * 20ms delay is needed.
+ÂÂÂÂÂÂÂÂ */
+ÂÂÂÂÂÂÂ usleep_range(20000, 20100);
+
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_OCP_DET_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_OCP_DET_ENABLE);
+ÂÂÂÂÂÂÂ /* Remove Mute on primary path */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0);
+ÂÂÂÂÂÂÂ /* Enable GM3 boost */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_GM3_BOOST_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_GM3_BOOST_ENABLE);
+ÂÂÂÂÂÂÂ /* Enable AutoChop timer at the end of power up */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_NEW_INT_HPH_TIMER1,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
+ÂÂÂÂÂÂÂ /* Remove mix path mute */
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case SND_SOC_DAPM_PRE_PMD:
+ÂÂÂÂÂÂÂ /* Enable DSD Mute before PA disable */
+
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_OCP_DET_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_HPH_OCP_DET_DISABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_PGA_MUTE_ENABLE);
+ÂÂÂÂÂÂÂ snd_soc_component_update_bits(comp,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ WCD934X_RX_PATH_PGA_MUTE_ENABLE);
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case SND_SOC_DAPM_POST_PMD:
+ÂÂÂÂÂÂÂ /*
+ÂÂÂÂÂÂÂÂ * 5ms sleep is required after PA disable. If compander is
+ÂÂÂÂÂÂÂÂ * disabled, then 20ms delay is needed after PA disable.
+ÂÂÂÂÂÂÂÂ */
+ÂÂÂÂÂÂÂÂÂÂÂ usleep_range(20000, 20100);
Superfluous identation.
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ };
+
+ÂÂÂ return 0;
+}
+
+static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct snd_kcontrol *kcontrol,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int event)
+{
+ÂÂÂ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+
+ÂÂÂ switch (event) {
+ÂÂÂ case SND_SOC_DAPM_PRE_PMU:
+ÂÂÂÂÂÂÂ break;
Redundant case.
+ÂÂÂ case SND_SOC_DAPM_POST_PMU:
+ÂÂÂÂÂÂÂ /*
+ÂÂÂÂÂÂÂÂ * 7ms sleep is required after PA is enabled as per
+ÂÂÂÂÂÂÂÂ * HW requirement. If compander is disabled, then
+ÂÂÂÂÂÂÂÂ * 20ms delay is needed.
+ÂÂÂÂÂÂÂÂ */
+ÂÂÂÂÂÂÂ usleep_range(20000, 20100);