Re: [PATCH v3 4/4] perf/core,x86: synchronize PMU task contexts on optimized context switches

[Alexey Budankov]

On 21.10.2019 10:59, Ingo Molnar wrote:
> 
> * Alexey Budankov <alexey.budankov@xxxxxxxxxxxxxxx> wrote:
> 
>> +			/*
>> +			 * PMU specific parts of task perf context may require
>> +			 * additional synchronization, at least for proper Intel
>> +			 * LBR callstack data profiling;
>> +			 */
>> +			pmu->sync_task_ctx(ctx->task_ctx_data,
>> +					   next_ctx->task_ctx_data);
> 
> Firstly, I'm pretty sure you never run this on a CPU where 
> pmu->sync_task_ctx is NULL, right? ;-)

Yes, right.

> 
> Secondly, even on Intel CPUs in many cases we'll just call into a ~2 deep 
> function pointer based call hierarchy, just to find that nothing needs to 
> be done, because there's no LBR call stack maintained:
> 
> +       if (!one || !another)
> +               return;
> 
> So while it's technically a layering violation, it might make sense to 
> elevate this check to the generic layer and say that synchronization 
> calls by the core layer will always provide two valid pointers?

This would also keep performance benefit of avoiding double indirect 
pointer calls for cases when LBR callstack is not requested.

As far it has the comment saying that check is intentionally placed 
at the core layer it doesn't look like a violation but rather 
performance optimization.

Let me come up with v4 to see how it would look like.

Thanks for observation, 
Alexey

> 
> Thanks,
> 
> 	Ingo
>