Re: linux-next: Tree for Oct 14 (insn_decoder_test)

[Masami Hiramatsu]

Hi,

On Mon, 14 Oct 2019 08:30:02 -0700
Randy Dunlap <rdunlap@xxxxxxxxxxxxx> wrote:

> On 10/13/19 11:47 PM, Stephen Rothwell wrote:
> > Hi all,
> > 
> > Changes since 20191011:
> > 
> 
> on x86_64:
> 
>   HOSTCC  arch/x86/tools/insn_decoder_test
>   HOSTCC  arch/x86/tools/insn_sanity
>   TEST    posttest
> arch/x86/tools/insn_decoder_test: warning: Found an x86 instruction decoder bug, please report this.
> arch/x86/tools/insn_decoder_test: warning: ffffffff81000bf1:	f7 0b 00 01 08 00    	testl  $0x80100,(%rbx)
> arch/x86/tools/insn_decoder_test: warning: objdump says 6 bytes, but insn_get_length() says 2
> arch/x86/tools/insn_decoder_test: warning: Decoded and checked 11913894 instructions with 1 failures
>   TEST    posttest
> arch/x86/tools/insn_sanity: Success: decoded and checked 1000000 random instructions with 0 errors (seed:0x871ce29c)

Hmm, curious.

x86-opcode-map.txt said,
f7: Grp3_2 Ev (1A)

and "0x0b" is 00001011b, Group encoding bits are 5,4,3 (reg field),
so group index is 001.

GrpTable: Grp3_2
0: TEST Ev,Iz
1:

Hmm, "f7 0b" is not assigned to any instruction... (testl should be f7 03)

I've checked Intel SDM May 2019 version(*), but the Opcode Map (Table A-6. Opecode
Extensions for One- and Two-byte Opecodes by Group Number) showed the group index
001 is still blank. I've also checked that Table B-13 (General Purpose Instruction
 Formats and Encodings for Non-64-Bit Modes (Note that this has no REX prefix)) but
I couldn't find "f7 0b".

At last, I found that on AMD64 Architecture Programmer's Manual Volume 3, Appendix A.2
Table A-6. ModRM.reg Extensions for the Primary Opcode Map(**), which shows that both
f7 + reg=000 and f7 + reg=001 are same. So only on AMD64, it is officially available
instruction.

(*) https://software.intel.com/sites/default/files/managed/a4/60/325383-sdm-vol-2abcd.pdf
(**) https://www.amd.com/system/files/TechDocs/24594.pdf

OK, so this should be fixed with below patch.

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