Re: [PATCH v3 1/2] arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear

[liwei (GF)]

Hi Marc,

On 2019/10/23 20:13, Marc Zyngier wrote:
> Hi Wei,
> 
> On 2019-10-23 09:38, liwei (GF) wrote:
>> Hi Marc,
>>
>> On 2019/10/2 17:06, Marc Zyngier wrote:
>>> The GICv3 architecture specification is incredibly misleading when it
>>> comes to PMR and the requirement for a DSB. It turns out that this DSB
>>> is only required if the CPU interface sends an Upstream Control
>>> message to the redistributor in order to update the RD's view of PMR.
>>>
>>> This message is only sent when ICC_CTLR_EL1.PMHE is set, which isn't
>>> the case in Linux. It can still be set from EL3, so some special care
>>> is required. But the upshot is that in the (hopefuly large) majority
>>> of the cases, we can drop the DSB altogether.
>>>
>>> This relies on a new static key being set if the boot CPU has PMHE
>>> set. The drawback is that this static key has to be exported to
>>> modules.
>>>
>>> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
>>> Cc: Will Deacon <will@xxxxxxxxxx>
>>> Cc: James Morse <james.morse@xxxxxxx>
>>> Cc: Julien Thierry <julien.thierry.kdev@xxxxxxxxx>
>>> Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>>> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
>>> ---
>>> Âarch/arm64/include/asm/barrier.hÂÂ | 12 ++++++++++++
>>> Âarch/arm64/include/asm/daifflags.h |Â 3 ++-
>>> Âarch/arm64/include/asm/irqflags.h | 19 ++++++++++---------
>>> Âarch/arm64/include/asm/kvm_host.h | 3 +--
>>> Âarch/arm64/kernel/entry.SÂÂÂÂÂÂÂÂÂ |Â 6 ++++--
>>> Âarch/arm64/kvm/hyp/switch.cÂÂÂÂÂÂÂ |Â 4 ++--
>>> Âdrivers/irqchip/irq-gic-v3.cÂÂÂÂÂÂ | 20 ++++++++++++++++++++
>>> Âinclude/linux/irqchip/arm-gic-v3.h |Â 2 ++
>>> Â8 files changed, 53 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
>>> index e0e2b1946f42..7d9cc5ec4971 100644
>>> --- a/arch/arm64/include/asm/barrier.h
>>> +++ b/arch/arm64/include/asm/barrier.h
>>> @@ -29,6 +29,18 @@
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SB_BARRIER_INSN"nop\n",ÂÂÂ \
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ARM64_HAS_SB))
>>>
>>> +#ifdef CONFIG_ARM64_PSEUDO_NMI
>>> +#define pmr_sync()ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ \
>>> +ÂÂÂ do {ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ \
>>> +ÂÂÂÂÂÂÂ extern struct static_key_false gic_pmr_sync;ÂÂÂ \
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ \
>>> +ÂÂÂÂÂÂÂ if (static_branch_unlikely(&gic_pmr_sync))ÂÂÂ \
>>> +ÂÂÂÂÂÂÂÂÂÂÂ dsb(sy);ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ \
>>> +ÂÂÂ } while(0)
>>> +#else
>>> +#define pmr_sync()ÂÂÂ do {} while (0)
>>> +#endif
>>> +
>>
>> Thank you for solving this problem, it helps a lot indeed.
>>
>> The pmr_sync() will call dsb(sy) when ARM64_PSEUDO_NMI=y and
>> gic_pmr_sync=force,
>> but if pseudo nmi is not enabled through boot option, it just take one more
>> redundant calling than before at the following two place.
>>
>> I think change dsb(sy) to
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ asm volatile(ALTERNATIVE("nop", "dsb sy",ÂÂÂÂ Â\
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ARM64_HAS_IRQ_PRIO_MASKING)ÂÂÂÂ \
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ : : : "memory");ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ \
>> may be more appropriate.
> 
> I'm not sure I understand what you mean. The static key defaults to false,
> so if pseudo_nmi is not enabled, this dsb(sy) is simply never executed.
> 
> Am I missing something obvious?
> 
> Thanks,
> 
> ÂÂÂÂÂÂÂ M.
> 
You are right, my mistake. Sorry for confusing you.

Thanks,
Wei