Re: [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link

From: Dilip Kota
Date: Tue Oct 29 2019 - 05:31:30 EST

On 10/22/2019 8:59 PM, Bjorn Helgaas wrote:
[+cc Rafael, linux-pm, beginning of discussion at]

On Tue, Oct 22, 2019 at 05:27:38PM +0800, Dilip Kota wrote:
On 10/22/2019 1:18 AM, Bjorn Helgaas wrote:
On Mon, Oct 21, 2019 at 02:38:50PM +0100, Andrew Murray wrote:
On Mon, Oct 21, 2019 at 02:39:20PM +0800, Dilip Kota wrote:
PCIe RC driver on Intel Gateway SoCs have a requirement
of changing link width and speed on the fly.
Please add more details about why this is needed. Since you're adding
sysfs files, it sounds like it's not actually the *driver* that needs
this; it's something in userspace?
We have use cases to change the link speed and width on the fly.
One is EMI check and other is power saving. Some battery backed
applications have to switch PCIe link from higher GEN to GEN1 and
width to x1. During the cases like external power supply got
disconnected or broken. Once external power supply is connected then
switch PCIe link to higher GEN and width.
That sounds plausible, but of course nothing there is specific to the
Intel Gateway, so we should implement this generically so it would
work on all hardware.

I'm not sure what the interface should look like -- should it be a
low-level interface as you propose where userspace would have to
identify each link of interest, or is there some system-wide
power/performance knob that could tune all links? Cc'd Rafael and
linux-pm in case they have ideas.

To my knowledge sysfs is the appropriate way to go.
If there are any other best possible knobs, will be helpful.