Re: [PATCH v2 2/2] clk: tegra: divider: Support enable-bit for Super clocks
From: Dmitry Osipenko
Date: Tue Oct 29 2019 - 09:20:42 EST
28.10.2019 17:41, Peter De Schrijver ÐÐÑÐÑ:
> On Tue, Jul 23, 2019 at 05:52:45AM +0300, Dmitry Osipenko wrote:
>> All Super clocks have a divider that has the enable bit.
> This is broken to begin with. The only clock of this type in upstream is SCLK
> I think. However, this clock is not a normal divider, it's a skipper, so
> the normal divider logic doesn't work for it. In practice this clock is
> only used when scaling SCLK, which is not (yet) done in the upstream
> kernel due to the complex DVFS relationship between sclk, hclk and pclk.
> A driver for it can be found here:
> As you can see in that tree, we eventually splitted sclk into three
> sclk_mux (controls SCLK_BURST_POLICY register)
> sclk (controls SOURCE_SYS register which is like a normal peripheral
> clock but without the mux)
> sclk_skipper (controls SCLK_DIVIDER)
I'll drop this patch, thanks again for the clarification.