Re: [PATCH v2 03/10] media: hantro: Fix picture order count table enable

[Boris Brezillon]

On Tue, 29 Oct 2019 01:24:48 +0000
Jonas Karlman <jonas@xxxxxxxxx> wrote:

> From: Francois Buergisser <fbuergisser@xxxxxxxxxxxx>
> 
> The picture order count table only makes sense for profiles
> higher than Baseline. This is confirmed by the H.264 specification
> (See 8.2.1 Decoding process for picture order count), which
> clarifies how POC are used for features not present in Baseline.
> 
> """
> Picture order counts are used to determine initial picture orderings
> for reference pictures in the decoding of B slices, to represent picture
> order differences between frames or fields for motion vector derivation
> in temporal direct mode, for implicit mode weighted prediction in B slices,
> and for decoder conformance checking.
> """
> 
> As a side note, this change matches various vendors downstream codebases,
> including ChromiumOS and IMX VPU libraries.
> 
> Fixes: dea0a82f3d22 ("media: hantro: Add support for H264 decoding on G1")
> Signed-off-by: Francois Buergisser <fbuergisser@xxxxxxxxxxxx>
> Signed-off-by: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxx>
> Signed-off-by: Jonas Karlman <jonas@xxxxxxxxx>

Reviewed-by: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxx>
Tested-by: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxx>

Same as for patch 2, it would be great to have this fix queued for
5.4-rc6 so we don't have to backport it manually.

> ---
>  drivers/staging/media/hantro/hantro_g1_h264_dec.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> index a1cb18680200..70a6b5b26477 100644
> --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> @@ -34,9 +34,11 @@ static void set_params(struct hantro_ctx *ctx)
>  	reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0);
>  	if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
>  		reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E;
> -	reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E;
> -	if (sps->profile_idc > 66 && dec_param->nal_ref_idc)
> -		reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E;
> +	if (sps->profile_idc > 66) {
> +		reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E;
> +		if (dec_param->nal_ref_idc)
> +			reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E;
> +	}
>  
>  	if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) &&
>  	    (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD ||