[PATCH] clk: qcom: gcc-sm8150: Drop non-DT fallback parent names

[Stephen Boyd]

The .name field of clk_parent_data should only be specified if the DT
node doesn't have the proper 'clocks' and 'clock-names' properties. For
this driver the DT has always had the correct properties so these fields
have been unnecessary.

Cc: Vinod Koul <vkoul@xxxxxxxxxx>
Cc: Taniya Das <tdas@xxxxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
---
 drivers/clk/qcom/gcc-sm8150.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 20877214acff..5165f4d0f004 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -49,7 +49,6 @@ static struct clk_alpha_pll gpll0 = {
 			.name = "gpll0",
 			.parent_data = &(const struct clk_parent_data){
 				.fw_name = "bi_tcxo",
-				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_trion_fixed_pll_ops,
@@ -76,7 +75,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
 		.name = "gpll0_out_even",
 		.parent_data = &(const struct clk_parent_data){
 			.fw_name = "bi_tcxo",
-			.name = "bi_tcxo",
 		},
 		.num_parents = 1,
 		.ops = &clk_trion_pll_postdiv_ops,
@@ -95,7 +93,6 @@ static struct clk_alpha_pll gpll7 = {
 			.name = "gpll7",
 			.parent_data = &(const struct clk_parent_data){
 				.fw_name = "bi_tcxo",
-				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_trion_fixed_pll_ops,
@@ -115,7 +112,6 @@ static struct clk_alpha_pll gpll9 = {
 			.name = "gpll9",
 			.parent_data = &(const struct clk_parent_data){
 				.fw_name = "bi_tcxo",
-				.name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_trion_fixed_pll_ops,
@@ -131,7 +127,7 @@ static const struct parent_map gcc_parent_map_0[] = {
 };
 
 static const struct clk_parent_data gcc_parents_0[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll0_out_even.clkr.hw },
 	{ .fw_name = "core_bi_pll_test_se" },
@@ -146,9 +142,9 @@ static const struct parent_map gcc_parent_map_1[] = {
 };
 
 static const struct clk_parent_data gcc_parents_1[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
-	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
+	{ .fw_name = "sleep_clk" },
 	{ .hw = &gpll0_out_even.clkr.hw },
 	{ .fw_name = "core_bi_pll_test_se" },
 };
@@ -160,8 +156,8 @@ static const struct parent_map gcc_parent_map_2[] = {
 };
 
 static const struct clk_parent_data gcc_parents_2[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
-	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
+	{ .fw_name = "bi_tcxo" },
+	{ .fw_name = "sleep_clk" },
 	{ .fw_name = "core_bi_pll_test_se" },
 };
 
@@ -172,7 +168,7 @@ static const struct parent_map gcc_parent_map_3[] = {
 };
 
 static const struct clk_parent_data gcc_parents_3[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .fw_name = "core_bi_pll_test_se"},
 };
@@ -183,7 +179,7 @@ static const struct parent_map gcc_parent_map_4[] = {
 };
 
 static const struct clk_parent_data gcc_parents_4[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .fw_name = "core_bi_pll_test_se" },
 };
 
@@ -196,7 +192,7 @@ static const struct parent_map gcc_parent_map_5[] = {
 };
 
 static const struct clk_parent_data gcc_parents_5[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll7.clkr.hw },
 	{ .hw = &gpll0_out_even.clkr.hw },
@@ -212,7 +208,7 @@ static const struct parent_map gcc_parent_map_6[] = {
 };
 
 static const struct clk_parent_data gcc_parents_6[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll9.clkr.hw },
 	{ .hw = &gpll0_out_even.clkr.hw },
@@ -228,9 +224,9 @@ static const struct parent_map gcc_parent_map_7[] = {
 };
 
 static const struct clk_parent_data gcc_parents_7[] = {
-	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .fw_name = "bi_tcxo" },
 	{ .hw = &gpll0.clkr.hw },
-	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
+	{ .fw_name = "aud_ref_clk" },
 	{ .hw = &gpll0_out_even.clkr.hw },
 	{ .fw_name = "core_bi_pll_test_se" },
 };
-- 
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