Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Dmitry Osipenko]

14.11.2019 02:03, Stephen Boyd ÐÐÑÐÑ:
> Quoting Dmitry Osipenko (2019-10-29 17:48:13)
>> UART clock is divided using divisor values from DLM/DLL registers when
>> enable-bit is unset in clk register and clk's divider configuration isn't
>> taken onto account in this case. This doesn't cause any problems, but
>> let's add a check for the divider's enable-bit state, for consistency.
>>
>> Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
>> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
>> ---
> 
> Is this going to be picked up or should I just apply atop the tegra PR?

Looks like this patch missed the Tegra's PR by accident.

Stephen, I assume it will be easier if you could apply this patch atop.
The patch doesn't have any dependencies on any other patches, so it's
fine to apply it separately. Thanks in advance!

Thierry, please let us know if you have any objections.