On Mon, 18 Nov 2019 21:55:03 +0100
Auger Eric <eric.auger@xxxxxxxxxx> wrote:
Hi Jacob,You are right, this check is not needed any more. I will drop the patch.
On 11/18/19 8:42 PM, Jacob Pan wrote:
When setting up first level page tables for sharing with CPU, weCan it happen? If I am not wrong intel_pasid_setup_first_level() only
need to ensure IOMMU can support no less than the levels supported
by the CPU.
It is not adequate, as in the current code, to set up 5-level paging
in PASID entry First Level Paging Mode(FLPM) solely based on CPU.
Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table
interface")
Signed-off-by: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
Acked-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
---
drivers/iommu/intel-pasid.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel-pasid.c
b/drivers/iommu/intel-pasid.c index 040a445be300..e7cb0b8a7332
100644 --- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct
intel_iommu *iommu, }
#ifdef CONFIG_X86
- if (cpu_feature_enabled(X86_FEATURE_LA57))
- pasid_set_flpm(pte, 1);
+ /* Both CPU and IOMMU paging mode need to match */
+ if (cpu_feature_enabled(X86_FEATURE_LA57)) {
+ if (cap_5lp_support(iommu->cap)) {
+ pasid_set_flpm(pte, 1);
+ } else {
+ pr_err("VT-d has no 5-level paging support
for CPU\n");
+ pasid_clear_entry(pte);
+ return -EINVAL;
seems to be called from intel_svm_bind_mm which now checks the
SVM_CAPABLE flag.
Thanks