Re: [PATCH V4 03/13] perf tools: Support new branch sample type for LBR TOS

[Peter Zijlstra]

On Tue, Nov 19, 2019 at 11:00:00AM -0800, Stephane Eranian wrote:
> On Tue, Nov 19, 2019 at 6:35 AM <kan.liang@xxxxxxxxxxxxxxx> wrote:

> > diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
> > index bb7b271397a6..c2da61c9ace7 100644
> > --- a/tools/include/uapi/linux/perf_event.h
> > +++ b/tools/include/uapi/linux/perf_event.h
> > @@ -180,7 +180,10 @@ enum perf_branch_sample_type_shift {
> >
> >         PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT      = 16, /* save branch type */
> >
> > -       PERF_SAMPLE_BRANCH_MAX_SHIFT            /* non-ABI */
> > +       PERF_SAMPLE_BRANCH_MAX_SHIFT            = 17, /* non-ABI */
> > +
> > +       /* PMU specific */
> 
> No! You must abstract this.
> 
> > +       PERF_SAMPLE_BRANCH_LBR_TOS_SHIFT        = 63, /* save LBR TOS */
> >  };
> >
> I don't like this because this is too Intel specific.
> What is the meaning of this field? You need a clear definition so it can be used
> with other PERF_SAMPLE_BRANCH_* implementations.

I also detest the MSB usage. Normal pattern is that any bit >= MAX
will be rejected by the kernel.