Re: [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask

[tanhuazhong]

Sorry, please ignore this patch.
Will resend later.

On 2019/11/20 9:44, Huazhong Tan wrote:
> According to hardware user manual, bits5~7 in register
> HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
> but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
> will make hclge_reset_err_handle() read the wrong reset
> interrupt status.
>
> This patch fixes this wrong bit mask.
>
> Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
> Signed-off-by: Huazhong Tan <tanhuazhong@xxxxxxxxxx>
> ---
>   drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> index 59b8243..615cde1 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> @@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE {
>   #define HCLGE_GLOBAL_RESET_BIT		0
>   #define HCLGE_CORE_RESET_BIT		1
>   #define HCLGE_IMP_RESET_BIT		2
> -#define HCLGE_RESET_INT_M		GENMASK(2, 0)
> +#define HCLGE_RESET_INT_M		GENMASK(7, 5)
>   #define HCLGE_FUN_RST_ING		0x20C00
>   #define HCLGE_FUN_RST_ING_B		0
>