[PATCH v3 1/2] usb: dwc3: Add chip-specific compatible string

[Ran Wang]

Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.

Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.

Signed-off-by: Ran Wang <ran.wang_1@xxxxxxx>
---
Change in v3:
	- Update commit subject according to content change, originanl one is
	  'usb: dwc3: Add node to update cache type setting'
	- Replace sub-node definition with chip-specifc compatible string.

Change in v2:
	- New file.

 Documentation/devicetree/bindings/usb/dwc3.txt | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a4..043c312e 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -4,7 +4,21 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
       as described in 'usb/generic.txt'
 
 Required properties:
- - compatible: must be "snps,dwc3"
+ - compatible: must be "snps,dwc3" and (if applicable) may contain a
+	chip-specific compatible string in front of it to allow dwc3 driver be
+	able to update cache type configuration accordingly, otherwise
+	Layerscape SoC will encounter USB init failure when adding property
+	dma-coherent on device tree.
+	Example:
+	* "fsl,ls1012a-dwc3", "snps,dwc3"
+	* "fsl,ls1021a-dwc3", "snps,dwc3"
+	* "fsl,ls1028a-dwc3", "snps,dwc3"
+	* "fsl,ls1043a-dwc3", "snps,dwc3"
+	* "fsl,ls1046a-dwc3", "snps,dwc3"
+	* "fsl,ls1088a-dwc3", "snps,dwc3"
+	* "fsl,ls2088a-dwc3", "snps,dwc3"
+	* "fsl,lx2160a-dwc3", "snps,dwc3"
+
  - reg : Address and length of the register set for the device
  - interrupts: Interrupts used by the dwc3 controller.
  - clock-names: should contain "ref", "bus_early", "suspend"
-- 
2.7.4