[PATCH 2/6] dt-bindings: reset: add bindings for rtd1619 reset controls

From: James Tai
Date: Tue Dec 03 2019 - 02:36:25 EST

From: cylee12 <cylee12@xxxxxxxxxxx>

Add devicetree binding for Realtek RTD1619 SoC reset controls.

Signed-off-by: Cheng-Yu Lee <cylee12@xxxxxxxxxxx>
Signed-off-by: James Tai <james.tai@xxxxxxxxxxx>
---
include/dt-bindings/reset/rtk,reset-rtd1619.h | 124 ++++++++++++++++++
1 file changed, 124 insertions(+)
create mode 100644 include/dt-bindings/reset/rtk,reset-rtd1619.h

diff --git a/include/dt-bindings/reset/rtk,reset-rtd1619.h b/include/dt-bindings/reset/rtk,reset-rtd1619.h
new file mode 100644
index 000000000000..f6fa6359ec1c
--- /dev/null
+++ b/include/dt-bindings/reset/rtk,reset-rtd1619.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __DT_BINDINGS_RTK_RESET_RTD1619_H
+#define __DT_BINDINGS_RTK_RESET_RTD1619_H
+
+#define CC_RSTN_REG_BANK_1 (0x0000)
+#define CC_RSTN_REG_BANK_2 (0x0100)
+#define CC_RSTN_REG_BANK_3 (0x0200)
+#define CC_RSTN_REG_BANK_4 (0x0300)
+#define CC_RSTN_REG_BANK_6 (0x0400)
+#define CC_RSTN_REG_BANK_7 (0x0500)
+
+#define CC_RSTN_MISC (CC_RSTN_REG_BANK_1 | 0x00)
+#define CC_RSTN_DIP (CC_RSTN_REG_BANK_1 | 0x02)
+#define CC_RSTN_GSPI (CC_RSTN_REG_BANK_1 | 0x04)
+#define CC_RSTN_SDS (CC_RSTN_REG_BANK_1 | 0x06)
+#define CC_RSTN_SDS_REG (CC_RSTN_REG_BANK_1 | 0x08)
+#define CC_RSTN_SDS_PHY (CC_RSTN_REG_BANK_1 | 0x0a)
+#define CC_RSTN_VE1 (CC_RSTN_REG_BANK_1 | 0x0c)
+#define CC_RSTN_VE2 (CC_RSTN_REG_BANK_1 | 0x0e)
+#define CC_RSTN_R2RDSC_A00 (CC_RSTN_REG_BANK_1 | 0x10)
+#define CC_RSTN_RSA (CC_RSTN_REG_BANK_1 | 0x12)
+#define CC_RSTN_GPU (CC_RSTN_REG_BANK_1 | 0x14)
+#define CC_RSTN_DC_PHY (CC_RSTN_REG_BANK_1 | 0x16)
+#define CC_RSTN_DCPHY_CRT (CC_RSTN_REG_BANK_1 | 0x18)
+#define CC_RSTN_LSADC (CC_RSTN_REG_BANK_1 | 0x1a)
+#define CC_RSTN_SE (CC_RSTN_REG_BANK_1 | 0x1c)
+#define CC_RSTN_HSE_A00 (CC_RSTN_REG_BANK_1 | 0x1e)
+
+#define CC_RSTN_JPEG (CC_RSTN_REG_BANK_2 | 0x00)
+#define CC_RSTN_SD (CC_RSTN_REG_BANK_2 | 0x02)
+#define CC_RSTN_EMMC_A00 (CC_RSTN_REG_BANK_2 | 0x04)
+#define CC_RSTN_SDIO (CC_RSTN_REG_BANK_2 | 0x06)
+#define CC_RSTN_PCR_CNT (CC_RSTN_REG_BANK_2 | 0x08)
+#define CC_RSTN_PCIE0_STITCH (CC_RSTN_REG_BANK_2 | 0x0a)
+#define CC_RSTN_PCIE0_PHY (CC_RSTN_REG_BANK_2 | 0x0c)
+#define CC_RSTN_PCIE0 (CC_RSTN_REG_BANK_2 | 0x0e)
+#define CC_RSTN_PCIE0_CORE (CC_RSTN_REG_BANK_2 | 0x10)
+#define CC_RSTN_PCIE0_POWER (CC_RSTN_REG_BANK_2 | 0x12)
+#define CC_RSTN_PCIE0_NONSTITCH (CC_RSTN_REG_BANK_2 | 0x14)
+#define CC_RSTN_PCIE0_PHY_MDIO (CC_RSTN_REG_BANK_2 | 0x16)
+#define CC_RSTN_PCIE0_SGMII_MDIO (CC_RSTN_REG_BANK_2 | 0x18)
+#define CC_RSTN_UR2 (CC_RSTN_REG_BANK_2 | 0x1a)
+#define CC_RSTN_UR1 (CC_RSTN_REG_BANK_2 | 0x1c)
+#define CC_RSTN_MISC_SC0 (CC_RSTN_REG_BANK_2 | 0x1e)
+
+#define CC_RSTN_AE (CC_RSTN_REG_BANK_3 | 0x00)
+#define CC_RSTN_CABLERX (CC_RSTN_REG_BANK_3 | 0x02)
+#define CC_RSTN_MD_A00 (CC_RSTN_REG_BANK_3 | 0x04)
+#define CC_RSTN_TP_A00 (CC_RSTN_REG_BANK_3 | 0x06)
+#define CC_RSTN_NF_A00 (CC_RSTN_REG_BANK_3 | 0x08)
+#define CC_RSTN_MISC_SC1 (CC_RSTN_REG_BANK_3 | 0x0a)
+#define CC_RSTN_I2C_3 (CC_RSTN_REG_BANK_3 | 0x0c)
+#define CC_RSTN_FAN (CC_RSTN_REG_BANK_3 | 0x0e)
+#define CC_RSTN_TVE (CC_RSTN_REG_BANK_3 | 0x10)
+#define CC_RSTN_AIO (CC_RSTN_REG_BANK_3 | 0x12)
+#define CC_RSTN_VO (CC_RSTN_REG_BANK_3 | 0x14)
+#define CC_RSTN_MIPI_A00 (CC_RSTN_REG_BANK_3 | 0x16)
+#define CC_RSTN_HDMIRX (CC_RSTN_REG_BANK_3 | 0x18)
+#define CC_RSTN_HDMIRX_WRAP (CC_RSTN_REG_BANK_3 | 0x1a)
+#define CC_RSTN_HDMI (CC_RSTN_REG_BANK_3 | 0x1c)
+#define CC_RSTN_DISP (CC_RSTN_REG_BANK_3 | 0x1e)
+
+#define CC_RSTN_SATA_PHY_POW1 (CC_RSTN_REG_BANK_4 | 0x00)
+#define CC_RSTN_SATA_PHY_POW0 (CC_RSTN_REG_BANK_4 | 0x02)
+#define CC_RSTN_SATA_MDIO1 (CC_RSTN_REG_BANK_4 | 0x04)
+#define CC_RSTN_SATA_MDIO0 (CC_RSTN_REG_BANK_4 | 0x06)
+#define CC_RSTN_SATA_WRAP (CC_RSTN_REG_BANK_4 | 0x08)
+#define CC_RSTN_SATA_MAC_P1 (CC_RSTN_REG_BANK_4 | 0x0a)
+#define CC_RSTN_SATA_MAC_P0 (CC_RSTN_REG_BANK_4 | 0x0c)
+#define CC_RSTN_SATA_MAC_COM (CC_RSTN_REG_BANK_4 | 0x0e)
+#define CC_RSTN_PCIE1_STITCH (CC_RSTN_REG_BANK_4 | 0x10)
+#define CC_RSTN_PCIE1_PHY (CC_RSTN_REG_BANK_4 | 0x12)
+#define CC_RSTN_PCIE1 (CC_RSTN_REG_BANK_4 | 0x14)
+#define CC_RSTN_PCIE1_CORE (CC_RSTN_REG_BANK_4 | 0x16)
+#define CC_RSTN_PCIE1_POWER (CC_RSTN_REG_BANK_4 | 0x18)
+#define CC_RSTN_PCIE1_NONSTITCH (CC_RSTN_REG_BANK_4 | 0x1a)
+#define CC_RSTN_PCIE1_PHY_MDIO (CC_RSTN_REG_BANK_4 | 0x1c)
+#define CC_RSTN_HDMITOP (CC_RSTN_REG_BANK_4 | 0x1e)
+
+#define CC_RSTN_HSE (CC_RSTN_REG_BANK_6 | 0x06)
+#define CC_RSTN_R2RDSC (CC_RSTN_REG_BANK_6 | 0x08)
+#define CC_RSTN_EMMC (CC_RSTN_REG_BANK_6 | 0x0a)
+#define CC_RSTN_NF (CC_RSTN_REG_BANK_6 | 0x0c)
+#define CC_RSTN_MD (CC_RSTN_REG_BANK_6 | 0x0e)
+#define CC_RSTN_TPB (CC_RSTN_REG_BANK_6 | 0x18)
+#define CC_RSTN_TP (CC_RSTN_REG_BANK_6 | 0x1a)
+#define CC_RSTN_MIPI (CC_RSTN_REG_BANK_6 | 0x1c)
+
+#define CC_RSTN_TPB_A00 (CC_RSTN_REG_BANK_7 | 0x00)
+#define CC_RSTN_I2C_4 (CC_RSTN_REG_BANK_7 | 0x02)
+#define CC_RSTN_I2C_5 (CC_RSTN_REG_BANK_7 | 0x04)
+#define CC_RSTN_TSIO (CC_RSTN_REG_BANK_7 | 0x06)
+#define CC_RSTN_VE3 (CC_RSTN_REG_BANK_7 | 0x08)
+#define CC_RSTN_EDP (CC_RSTN_REG_BANK_7 | 0x0a)
+
+/* 0x98007088 */
+#define IC_RSTN_VFD 0x0000
+#define IC_RSTN_IR 0x0001
+#define IC_RSTN_CEC0 0x0002
+#define IC_RSTN_CEC1 0x0003
+#define IC_RSTN_DP 0x0004
+#define IC_RSTN_CBUSTX 0x0005
+#define IC_RSTN_CBUSRX 0x0006
+#define IC_RSTN_EFUSE 0x0007
+#define IC_RSTN_UR0 0x0008
+#define IC_RSTN_GMAC 0x0009
+#define IC_RSTN_GPHY 0x000a
+#define IC_RSTN_I2C_0 0x000b
+#define IC_RSTN_I2C_1 0x000c
+#define IC_RSTN_CBUS 0x000d
+#define IC_RSTN_USB_DRD 0x000e
+#define IC_RSTN_USB_HOST 0x000f
+#define IC_RSTN_USB_PHY_0 0x0010
+#define IC_RSTN_USB_PHY_1 0x0011
+#define IC_RSTN_USB_PHY_2 0x0012
+#define IC_RSTN_USB 0x0013
+#define IC_RSTN_TYPE_C 0x0014
+#define IC_RSTN_USB_U3_HOST 0x0015
+#define IC_RSTN_USB3_PHY0_POW 0x0016
+#define IC_RSTN_USB3_P0_MDIO 0x0017
+#define IC_RSTN_USB3_PHY1_POW 0x0018
+#define IC_RSTN_USB3_P1_MDIO 0x0019
+
+#endif
--
2.24.0