Re: [PATCH v2 2/2] drm/komeda: Enable new product D32 support

From: james qian wang (Arm Technology China)
Date: Thu Dec 05 2019 - 03:53:23 EST

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In reply to: Mihail Atanassov: "Re: [PATCH v2 2/2] drm/komeda: Enable new product D32 support"
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On Tue, Dec 03, 2019 at 09:59:57AM +0000, Mihail Atanassov wrote:
> On Tuesday, 3 December 2019 06:46:06 GMT james qian wang (Arm Technology China) wrote:
> > On Mon, Dec 02, 2019 at 11:07:52AM +0000, Mihail Atanassov wrote:
> > > On Thursday, 21 November 2019 08:17:45 GMT james qian wang (Arm Technology China) wrote:
> > > > D32 is simple version of D71, the difference is:
> > > > - Only has one pipeline
> > > > - Drop the periph block and merge it to GCU
> > > >
> > > > v2: Rebase.
> > > >
> > > > Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@xxxxxxx>
> > > > ---
> > > > .../drm/arm/display/include/malidp_product.h | 3 +-
> > > > .../arm/display/komeda/d71/d71_component.c | 2 +-
> > > > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 43 ++++++++++++-------
> > > > .../gpu/drm/arm/display/komeda/d71/d71_regs.h | 13 ++++++
> > > > .../gpu/drm/arm/display/komeda/komeda_drv.c | 1 +
> > > > 5 files changed, 44 insertions(+), 18 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/arm/display/include/malidp_product.h b/drivers/gpu/drm/arm/display/include/malidp_product.h
> > > > index 96e2e4016250..dbd3d4765065 100644
> > > > --- a/drivers/gpu/drm/arm/display/include/malidp_product.h
> > > > +++ b/drivers/gpu/drm/arm/display/include/malidp_product.h
> > > > @@ -18,7 +18,8 @@
> > > > #define MALIDP_CORE_ID_STATUS(__core_id) (((__u32)(__core_id)) & 0xFF)
> > > >
> > > > /* Mali-display product IDs */
> > > > -#define MALIDP_D71_PRODUCT_ID 0x0071
> > > > +#define MALIDP_D71_PRODUCT_ID 0x0071
> > > > +#define MALIDP_D32_PRODUCT_ID 0x0032
> > > >
> > > > union komeda_config_id {
> > > > struct {
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > index 6dadf4413ef3..c7f7e9c545c7 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > @@ -1274,7 +1274,7 @@ static int d71_timing_ctrlr_init(struct d71_dev *d71,
> > > >
> > > > ctrlr = to_ctrlr(c);
> > > >
> > > > - ctrlr->supports_dual_link = true;
> > > > + ctrlr->supports_dual_link = d71->supports_dual_link;
> > > >
> > > > return 0;
> > > > }
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > index 9b3bf353b6cc..2d429e310e5b 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > @@ -371,23 +371,33 @@ static int d71_enum_resources(struct komeda_dev *mdev)
> > > > goto err_cleanup;
> > > > }
> > > >
> > > > - /* probe PERIPH */
> > > > + /* Only the legacy HW has the periph block, the newer merges the periph
> > > > + * into GCU
> > > > + */
> > > > value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);
> > > > - if (BLOCK_INFO_BLK_TYPE(value) != D71_BLK_TYPE_PERIPH) {
> > > > - DRM_ERROR("access blk periph but got blk: %d.\n",
> > > > - BLOCK_INFO_BLK_TYPE(value));
> > > > - err = -EINVAL;
> > > > - goto err_cleanup;
> > > > + if (BLOCK_INFO_BLK_TYPE(value) != D71_BLK_TYPE_PERIPH)
> > > > + d71->periph_addr = NULL;
> > > > +
> > > > + if (d71->periph_addr) {
> > > > + /* probe PERIPHERAL in legacy HW */
> > > > + value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
> > > > +
> > > > + d71->max_line_size = value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
> > > > + d71->max_vsize = 4096;
> > > > + d71->num_rich_layers = value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
> > > > + d71->supports_dual_link = !!(value & PERIPH_SPLIT_EN);
> > > > + d71->integrates_tbu = !!(value & PERIPH_TBU_EN);
> > > > + } else {
> > > > + value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID0);
> > > > + d71->max_line_size = GCU_MAX_LINE_SIZE(value);
> > > > + d71->max_vsize = GCU_MAX_NUM_LINES(value);
> > > > +
> > > > + value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID1);
> > > > + d71->num_rich_layers = GCU_NUM_RICH_LAYERS(value);
> > > > + d71->supports_dual_link = GCU_DISPLAY_SPLIT_EN(value);
> > > > + d71->integrates_tbu = GCU_DISPLAY_TBU_EN(value);
> > > > }
> > > >
> > > > - value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
> > > > -
> > > > - d71->max_line_size = value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
> > > > - d71->max_vsize = 4096;
> > > > - d71->num_rich_layers = value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
> > > > - d71->supports_dual_link = value & PERIPH_SPLIT_EN ? true : false;
> > > > - d71->integrates_tbu = value & PERIPH_TBU_EN ? true : false;
> > > > -
> > > > for (i = 0; i < d71->num_pipelines; i++) {
> > > > pipe = komeda_pipeline_add(mdev, sizeof(struct d71_pipeline),
> > > > &d71_pipeline_funcs);
> > > > @@ -415,7 +425,7 @@ static int d71_enum_resources(struct komeda_dev *mdev)
> > > > }
> > > >
> > > > /* loop the register blks and probe */
> > > > - i = 2; /* exclude GCU and PERIPH */
> > > > + i = 1; /* exclude GCU */
> > > > offset = D71_BLOCK_SIZE; /* skip GCU */
> > > > while (i < d71->num_blocks) {
> > > > blk_base = mdev->reg_base + (offset >> 2);
> > > > @@ -425,9 +435,9 @@ static int d71_enum_resources(struct komeda_dev *mdev)
> > > > err = d71_probe_block(d71, &blk, blk_base);
> > > > if (err)
> > > > goto err_cleanup;
> > > > - i++;
> > > > }
> > > >
> > > > + i++;
> > >
> > > This change doesn't make much sense if you want to count how many
> > > blocks are available, since you're now counting the reserved ones, too.
> >
> > That's because for D32 num_blocks includes the reserved blocks.
> >
> > > On the counting note, the prior code rides on the assumption the periph
> > > block is last in the map, and I don't see how you still handle not
> > > counting it in the D71 case.
> >
> > Since D71 has one reserved block, and now we count reserved block.
> >
> > So now no matter D32 or D71:
> > num_blocks = n_valid_block + n_reserved_block + GCU.
>
> So at least we need that comment dropped in with the code. Future HW
> might break your assumption here once more and it will then be useful
> to know why this works for both products.

OK, will add a comments like.

/* Per HW design: num_blocks = n_valid_block + n_reserved_block + GCU */

And Per HW, all arch-v1.x include (d71/d32/d77) follows this rule,
the old logic which skip the reserved-block actually not right.

> I'd personally abstract that a bit behind a small helper func and
> handle different products separately. It's a bit of duplication but
> much easier to comprehend. Saved cycles reading code == Good Thing(tm).

Our komeda driver has two layers, common layer and chip. current we
only have one chip folder d71 for support arch-v1.x prodcut.
And our future products (arch-v2.x) will have its own chip folder, and
its own chip specific code.

Thanks
James
>
> >
> > Thanks
> > James
> > >
> > > > offset += D71_BLOCK_SIZE;
> > > > }
> > > >
> > > > @@ -603,6 +613,7 @@ d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
> > > >
> > > > switch (product_id) {
> > > > case MALIDP_D71_PRODUCT_ID:
> > > > + case MALIDP_D32_PRODUCT_ID:
> > > > funcs = &d71_chip_funcs;
> > > > break;
> > > > default:
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h b/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > > > index 1727dc993909..81de6a23e7f3 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > > > @@ -72,6 +72,19 @@
> > > > #define GCU_CONTROL_MODE(x) ((x) & 0x7)
> > > > #define GCU_CONTROL_SRST BIT(16)
> > > >
> > > > +/* GCU_CONFIGURATION registers */
> > > > +#define GCU_CONFIGURATION_ID0 0x100
> > > > +#define GCU_CONFIGURATION_ID1 0x104
> > > > +
> > > > +/* GCU configuration */
> > > > +#define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF)
> > > > +#define GCU_MAX_NUM_LINES(x) ((x) >> 16)
> > > > +#define GCU_NUM_RICH_LAYERS(x) ((x) & 0x7)
> > > > +#define GCU_NUM_PIPELINES(x) (((x) >> 3) & 0x7)
> > > > +#define GCU_NUM_SCALERS(x) (((x) >> 6) & 0x7)
> > > > +#define GCU_DISPLAY_SPLIT_EN(x) (((x) >> 16) & 0x1)
> > > > +#define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)
> > > > +
> > > > /* GCU opmode */
> > > > #define INACTIVE_MODE 0
> > > > #define TBU_CONNECT_MODE 1
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
> > > > index b7a1097c45c4..ad38bbc7431e 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
> > > > @@ -125,6 +125,7 @@ static int komeda_platform_remove(struct platform_device *pdev)
> > > >
> > > > static const struct of_device_id komeda_of_match[] = {
> > > > { .compatible = "arm,mali-d71", .data = d71_identify, },
> > > > + { .compatible = "arm,mali-d32", .data = d71_identify, },
> > > > {},
> > > > };
> > > >
> > > >
> > >
> > >
> >
>
>
> --
> Mihail
>
>

Next message: Alexander Potapenko: "Re: kmsan boot error: KMSAN: uninit-value in proc_task_name"
Previous message: Chen-Yu Tsai: "[PATCH] rtc: sun6i: Add support for RTC clocks on R40"
In reply to: Mihail Atanassov: "Re: [PATCH v2 2/2] drm/komeda: Enable new product D32 support"
Next in thread: Mihail Atanassov: "Re: [PATCH v2 2/2] drm/komeda: Enable new product D32 support"
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