Re: [PATCH] RISC-V: Typo fixes in image header and documentation.

[Palmer Dabbelt]

On Tue, 26 Nov 2019 14:02:20 PST (-0800), Atish Patra wrote:
> On Tue, 2019-10-08 at 18:06 -0700, Atish Patra wrote:
> > There are some typos in boot image header and riscv boot
> > documentation.
> >
> > Fix the typos.
> >
> > Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
> > ---
> >  Documentation/riscv/boot-image-header.rst | 4 ++--
> >  arch/riscv/include/asm/image.h            | 4 ++--
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/riscv/boot-image-header.rst
> > b/Documentation/riscv/boot-image-header.rst
> > index 7b4d1d747585..8efb0596a33f 100644
> > --- a/Documentation/riscv/boot-image-header.rst
> > +++ b/Documentation/riscv/boot-image-header.rst
> > @@ -22,7 +22,7 @@ The following 64-byte header is present in
> > decompressed Linux kernel image::
> >  	u64 res2 = 0;		  /* Reserved */
> >  	u64 magic = 0x5643534952; /* Magic number, little endian,
> > "RISCV" */
> >  	u32 magic2 = 0x56534905;  /* Magic number 2, little endian,
> > "RSC\x05" */
> > -	u32 res4;		  /* Reserved for PE COFF offset */
> > +	u32 res3;		  /* Reserved for PE COFF offset */
> >  
> >  This header format is compliant with PE/COFF header and largely
> > inspired from
> >  ARM64 header. Thus, both ARM64 & RISC-V header can be combined into
> > one common
> > @@ -34,7 +34,7 @@ Notes
> >  - This header can also be reused to support EFI stub for RISC-V in
> > future. EFI
> >    specification needs PE/COFF image header in the beginning of the
> > kernel image
> >    in order to load it as an EFI application. In order to support EFI
> > stub,
> > -  code0 should be replaced with "MZ" magic string and res5(at offset
> > 0x3c) should
> > +  code0 should be replaced with "MZ" magic string and res3(at offset
> > 0x3c) should
> >    point to the rest of the PE/COFF header.
> >  
> >  - version field indicate header version number
> > diff --git a/arch/riscv/include/asm/image.h
> > b/arch/riscv/include/asm/image.h
> > index 344db5244547..4f8061a5ac4a 100644
> > --- a/arch/riscv/include/asm/image.h
> > +++ b/arch/riscv/include/asm/image.h
> > @@ -42,7 +42,7 @@
> >   * @res2:		reserved
> >   * @magic:		Magic number (RISC-V specific; deprecated)
> >   * @magic2:		Magic number 2 (to match the ARM64 'magic'
> > field pos)
> > - * @res4:		reserved (will be used for PE COFF offset)
> > + * @res3:		reserved (will be used for PE COFF offset)
> >   *
> >   * The intention is for this header format to be shared betweenres4
> > multiple
> >   * architectures to avoid a proliferation of image header formats.
> > @@ -59,7 +59,7 @@ struct riscv_image_header {
> >  	u64 res2;
> >  	u64 magic;
> >  	u32 magic2;
> > -	u32 res4;
> > +	u32 res3;
> >  };
> >  #endif /* __ASSEMBLY__ */
> >  #endif /* __ASM_IMAGE_H */
>
> ping ?

Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>

I'm assuming this is not going in through the RISC-V tree as it mostly touches
Documentation/.