Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver

[Dmitry Osipenko]

07.12.2019 18:53, Dmitry Osipenko ÐÐÑÐÑ:
> 07.12.2019 18:47, Dmitry Osipenko ÐÐÑÐÑ:
>> 07.12.2019 17:28, Dmitry Osipenko ÐÐÑÐÑ:
>>> 06.12.2019 05:48, Sowjanya Komatineni ÐÐÑÐÑ:
>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with
>>>> mux and gate for each of these clocks.
>>>>
>>>> Currently these PMC clocks are registered by Tegra clock driver using
>>>> clk_register_mux and clk_register_gate by passing PMC base address
>>>> and register offsets and PMC programming for these clocks happens
>>>> through direct PMC access by the clock driver.
>>>>
>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>> non-secure world does not go through and these clocks will not be
>>>> functional.
>>>>
>>>> This patch adds these clocks registration with PMC as a clock provider
>>>> for these clocks. clk_ops callback implementations for these clocks
>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
>>>> in secure mode and non-secure mode.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
>>>> ---
>>
>> [snip]
>>
>>>> +
>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>> +	.is_enabled = pmc_clk_is_enabled,
>>>> +	.enable = pmc_clk_enable,
>>>> +	.disable = pmc_clk_disable,
>>>> +};
>>>
>>> What's the benefit of separating GATE from the MUX?
>>>
>>> I think it could be a single clock.
>>
>> According to TRM:
>>
>> 1. GATE and MUX are separate entities.
>>
>> 2. GATE is the parent of MUX (see PMC's CLK_OUT paths diagram in TRM).
>>
>> 3. PMC doesn't gate EXTPERIPH clock but could "force-enable" it, correct?
> 
> 4. clk_m_div2/4 are internal PMC OSC dividers and thus these clocks
> should belong to PMC.

Also, it should be "osc" and not "clk_m".