Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt
From: Marc Zyngier
Date: Mon Dec 09 2019 - 10:36:42 EST
On 2019-12-09 15:25, Hannes Reinecke wrote:
On 12/9/19 4:17 PM, Marc Zyngier wrote:
On 2019-12-09 15:09, Hannes Reinecke wrote:
My idea here is slightly different: can't we leverage SMT?
I only know two of those: Cavium TX2 and ARM Neoverse-E1.
Most modern CPUs do SMT (I guess even ARM does it nowadays)
(Yes, I know about spectre and things. We're talking performance
ARM SMT CPUs are the absolute minority (and I can't say I'm
Ach, too bad.
Still a nice idea, putting SMT finally to some use ...
But isn't your SMT idea just a special case of providing an affinity
for the thread (and in this case relative to the affinity of the hard
You could apply the same principle to target any CPU affinity, and
provide hints for the placement if you're really keen (same L3, for
Jazz is not dead. It just smells funny...