Re: [PATCH] arm64: dts: a1: add saradc controller

From: Xingyu Chen
Date: Mon Dec 09 2019 - 22:57:12 EST

Hi, Kevin

On 2019/12/10 6:56, Kevin Hilman wrote:
Xingyu Chen <xingyu.chen@xxxxxxxxxxx> writes:

The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
so we use the same compatible string.

Signed-off-by: Xingyu Chen <xingyu.chen@xxxxxxxxxxx>

This patch is based on A1 clock patchset at [0].

arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..cad1756 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,21 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ saradc: adc@2c00 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x2c00 0x0 0x48>;
Why 0x48 here? AXG uses 0x38 and you're not adding any more registers
to this driver.

Thanks for you review.

The saradc introduces 4 new registers (as shown below) begin with g12a platform, and these registers are used
to save the sampling value of corresponding channel. In other words, we can choose fifo or new registers to save
sampling value, but it is not supported by the current driver.

dout register |---> fifo

AO_SAR_ADC_CHNL01ïsaving sampling data of channel 0/1
AO_SAR_ADC_CHNL23:ÂÂ saving sampling data of channel 2/3
AO_SAR_ADC_CHNL45:ÂÂ saving sampling data of channel 4/5
AO_SAR_ADC_CHNL67:ÂÂ saving sampling data of channel 6/7

This patch use the 0x48 to describe the registers length just follow the file meson-g12-common.dtsi. and it doesn't
affect the driver because of the mapped regiter length is limited by max_register member in struct regmap_config.

I can replace 0x48 with 0x38 in next patch if necessary.