Can you give the following a go? It probably has all kind of warts onCool, I anticipate that it should help my case.The ITS code will make the lowest online CPU in the affinity maskIf what you want is for the*default* affinity to be spread around,
the
target CPU for the interrupt, which may result in some CPUs
handling
so many interrupts.
that should be achieved pretty easily. Let me have a think about how
to do that.
I can also seek out some NVMe cards to see how it would help a more
"generic" scenario.
top of the quality debug information, but I managed to get my D05 and
a couple of guests to boot with it. It will probably eat your data,
so use caution!;-)
Thanks,
M.
diff --git a/drivers/irqchip/irq-gic-v3-its.c
b/drivers/irqchip/irq-gic-v3-its.c
index e05673bcd52b..301ee3bc0602 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -177,6 +177,8 @@ static DEFINE_IDA(its_vpeid_ida);