Re: [PATCH V5 RESEND 00/14] TopDown metrics support for Icelake

From: Liang, Kan
Date: Thu Dec 12 2019 - 08:47:32 EST

Hi Peter,

Could you please take a look at the patch set? If there is anything needs to be improved, please let me know.


On 12/3/2019 9:11 AM, kan.liang@xxxxxxxxxxxxxxx wrote:
From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>

Icelake has support for measuring the level 1 TopDown metrics
directly in hardware. This is implemented by an additional METRICS
register, and a new Fixed Counter 3 that measures pipeline SLOTS.

New in Icelake
- Do not require generic counters. This allows to collect TopDown always
in addition to other events.
- Measuring TopDown per thread/process instead of only per core

For the Ice Lake implementation of performance metrics, the values in
PERF_METRICS MSR are derived from fixed counter 3. Software should start
both registers, PERF_METRICS and fixed counter 3, from zero.
Additionally, software is recommended to periodically clear both
registers in order to maintain accurate measurements. The latter is
required for certain scenarios that involve sampling metrics at high
rates. Software should always write fixed counter 3 before write to

IA32_PERF_GLOBAL_STATUS. OVF_PERF_METRICS[48]: If this bit is set,
it indicates that some PERF_METRICS-related counter has overflowed and
a PMI is triggered. Software has to synchronize, e.g. re-start,
PERF_METRICS as well as fixed counter 3. Otherwise, PERF_METRICS may
return invalid values.

- To get accurate result and avoid reading the METRICS register multiple
times, the TopDown metrics events and SLOTS event have to be in the
same group.
- METRICS and SLOTS registers have to be cleared after each read by SW.
That is to prevent the lose of precision.
- Cannot do sampling read SLOTS and TopDown metric events

Please refer SDM Vol3, Performance Metrics for the details of
TopDown metrics.

Changes since V4:
- Add description regarding to event-code naming for fixed counters
- Fix add_nr_metric_event().
For leader event, we have to take the accepted metrics events into
For sibling event, it doesn't need to count accepted metrics events
- Remove is_first_topdown_event_in_group().
Force slots in topdown group. Only update topdown events with slots
- Re-use last_period and period_left for saved_metric and saved_slots.

Changes since V3:
- Separate fixed counter3 definition patch
- Separate BTS index patch
- Apply Peter's cleanup patch
- Fix the name of perf capabilities for perf METRICS
- Apply patch for mul_u64_u32_div() x86_64 implementation
- Fix unconditionally allows collecting 4 extra events
- Add patch to clean up NMI handler by naming global status bit
- Add patch to reuse event_base_rdpmc for RDPMC userspace support

Changes since V2:
- Rebase on top of v5.3-rc1

Key changes since V1:
- Remove variables for reg_idx and enabled_events[] array.
The reg_idx can be calculated by idx in runtime.
Using existing active_mask to replace enabled_events.
- Choose value 47 for the fixed index of BTS.
- Support OVF_PERF_METRICS overflow bit in PMI handler
- Drops the caching mechanism and related variables
New mechanism is to update all active slots/metrics events for the
first slots/metrics events in a group. For each group reading, it
still only read the slots/perf_metrics MSR once
- Disable PMU for read of topdown events to avoid the NMI issue
- Move RDPMC support to a separate patch
- Using event=0x00,umask=0x1X for topdown metrics events
- Drop the patch which add REMOVE transaction
We can indicate x86_pmu_stop() by checking
(event && !test_bit(event->hw.idx, cpuc->active_mask)),
which is a good place to save the slots/metrics MSR value

Andi Kleen (2):
perf, tools, stat: Support new per thread TopDown metrics
perf, tools: Add documentation for topdown metrics

Kan Liang (12):
perf/x86/intel: Introduce the fourth fixed counter
perf/x86/intel: Set correct mask for TOPDOWN.SLOTS
perf/x86/intel: Move BTS index to 47
perf/x86/intel: Basic support for metrics counters
perf/x86/intel: Fix the name of perf capabilities for perf METRICS
perf/x86/intel: Support hardware TopDown metrics
perf/x86/intel: Support per thread RDPMC TopDown metrics
perf/x86/intel: Export TopDown events for Icelake
perf/x86/intel: Disable sampling read slots and topdown
perf/x86/intel: Name global status bit in NMI handler
perf/x86: Use event_base_rdpmc for RDPMC userspace support
perf, tools, stat: Check Topdown Metric group

arch/x86/events/core.c | 86 +++++-
arch/x86/events/intel/core.c | 399 ++++++++++++++++++++++---
arch/x86/events/perf_event.h | 57 +++-
arch/x86/include/asm/msr-index.h | 3 +
arch/x86/include/asm/perf_event.h | 60 +++-
include/linux/perf_event.h | 29 +-
tools/perf/Documentation/perf-stat.txt | 9 +-
tools/perf/Documentation/topdown.txt | 235 +++++++++++++++
tools/perf/builtin-stat.c | 97 ++++++
tools/perf/util/stat-shadow.c | 89 ++++++
tools/perf/util/stat.c | 4 +
tools/perf/util/stat.h | 8 +
12 files changed, 1007 insertions(+), 69 deletions(-)
create mode 100644 tools/perf/Documentation/topdown.txt