Re: [PATCH v4 1/6] dt-bindings: clock: meson: add A1 PLL clock controller bindings

[Jian Hu]

On 2019/12/12 17:57, Jerome Brunet wrote:
> On Fri 06 Dec 2019 at 08:40, Jian Hu <jian.hu@xxxxxxxxxxx> wrote:
>
> > Add the documentation to support Amlogic A1 PLL clock driver,
> > and add A1 PLL clock controller bindings.
> >
> > Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
> > ---
> >   .../bindings/clock/amlogic,a1-pll-clkc.yaml   | 59 +++++++++++++++++++
> >   include/dt-bindings/clock/a1-pll-clkc.h       | 16 +++++
> >   2 files changed, 75 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> >   create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > new file mode 100644
> > index 000000000000..7feeef5abf1b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > @@ -0,0 +1,59 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>
> Rob commented on the above in v1 and it remains unaddressedOK, I will fix it in the next version.
>
> > +/*
> > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> > + */
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#";
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> > +
> > +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
> > +
> > +maintainers:
> > +  - Neil Armstrong <narmstrong@xxxxxxxxxxxx>
> > +  - Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> > +  - Jian Hu <jian.hu@xxxxxxxxxxx>
> > +
> > +properties:
> > +  compatible:
> > +    - enum:
> > +        - amlogic,a1-pll-clkc
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +clocks:
> > +  minItems: 2
> > +  maxItems: 2
> > +  items:
> > +   - description: Input xtal_fixpll
> > +   - description: Input xtal_hifipll
> > +
> > +clock-names:
> > +  minItems: 2
> > +  maxItems: 2
> > +  items:
> > +     - const: xtal_fixpll
> > +     - const: xtal_hifipll
> > +
> > +required:
> > +  - compatible
> > +  - "#clock-cells"
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    clkc_pll: pll-clock-controller@7c80 {
> > +                compatible = "amlogic,a1-pll-clkc";
> > +                reg = <0 0x7c80 0 0x18c>;
> > +                #clock-cells = <1>;
> > +                clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
> > +                         <&clkc_periphs CLKID_XTAL_HIFIPLL>;
> > +                clock-names = "xtal_fixpll", "xtal_hifipll";
> > +    };
> > diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
> > new file mode 100644
> > index 000000000000..58eae237e503
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/a1-pll-clkc.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> > + */
> > +
> > +#ifndef __A1_PLL_CLKC_H
> > +#define __A1_PLL_CLKC_H
> > +
> > +#define CLKID_FIXED_PLL				1
> > +#define CLKID_FCLK_DIV2				6
> > +#define CLKID_FCLK_DIV3				7
> > +#define CLKID_FCLK_DIV5				8
> > +#define CLKID_FCLK_DIV7				9
> > +#define CLKID_HIFI_PLL				10
> > +
> > +#endif /* __A1_PLL_CLKC_H */
>
> .