Re: [PATCH v3 1/5] clk: Ingenic: Remove unnecessary spinlock when reading registers.

[Zhou Yanjie]

Hi Paul,

On 2019å12æ15æ 02:07, Paul Cercueil wrote:
> Hi Zhou,
>
> You can also remove the locks around ingenic_cgu_gate_get(), they are 
> useless. Then also edit the doc of this function as currently it says 
> that the caller must hold the lock.

Sure, I'll remove it in v4.

Thanks and best regards!

> -Paul
>
>
> Le sam., dÃc. 14, 2019 at 23:33, åçæ (Zhou Yanjie) 
> <zhouyanjie@xxxxxxxxxxxxxx> a Ãcrit :
> > It is not necessary to use spinlock when reading registers,
> > so remove it from cgu.c.
> >
> > Suggested-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> > Suggested-by: Paul Burton <paulburton@xxxxxxxxxx>
> > Signed-off-by: åçæ (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
> > ---
> >
> > Notes:
> >     v2:
> >     New patch.
> >
> >     v2->v3:
> >     Adjust order from [5/5] in v2 to [1/5] in v3.
> >
> >  drivers/clk/ingenic/cgu.c | 6 ------
> >  1 file changed, 6 deletions(-)
> >
> > diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> > index 6e96303..8bd3998 100644
> > --- a/drivers/clk/ingenic/cgu.c
> > +++ b/drivers/clk/ingenic/cgu.c
> > @@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, 
> > unsigned long parent_rate)
> >      const struct ingenic_cgu_pll_info *pll_info;
> >      unsigned m, n, od_enc, od;
> >      bool bypass;
> > -    unsigned long flags;
> >      u32 ctl;
> >
> >      clk_info = &cgu->clock_info[ingenic_clk->idx];
> >      BUG_ON(clk_info->type != CGU_CLK_PLL);
> >      pll_info = &clk_info->pll;
> >
> > -    spin_lock_irqsave(&cgu->lock, flags);
> >      ctl = readl(cgu->base + pll_info->reg);
> > -    spin_unlock_irqrestore(&cgu->lock, flags);
> >
> >      m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
> >      m += pll_info->m_offset;
> > @@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw 
> > *hw)
> >      struct ingenic_cgu *cgu = ingenic_clk->cgu;
> >      const struct ingenic_cgu_clk_info *clk_info = 
> > to_clk_info(ingenic_clk);
> >      const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
> > -    unsigned long flags;
> >      u32 ctl;
> >
> > -    spin_lock_irqsave(&cgu->lock, flags);
> >      ctl = readl(cgu->base + pll_info->reg);
> > -    spin_unlock_irqrestore(&cgu->lock, flags);
> >
> >      return !!(ctl & BIT(pll_info->enable_bit));
> >  }
> > --
> > 2.7.4